公开(公告)号：US08129262B1

公开(公告)日：2012-03-06

申请号：US12607041

申请日：2009-10-27

Applicant: Constantin Bulucea ,  Fu-Cheng Wang ,  Prasad Chaparala

Inventor： Constantin Bulucea ,  Fu-Cheng Wang ,  Prasad Chaparala

IPC: H01L21/04

CPC classification number: H01L29/1083 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/105

Abstract: Fabrication of an insulated-gate field-effect transistor (110) entails separately introducing three body-material dopants, typically through an opening in a mask, into body material (50) of a semiconductor body so as to reach respective maximum dopant concentrations at three different vertical locations in the body material. A gate electrode (74) is subsequently defined after which a pair of source/drain zones (60 and 62), each having a main portion (60M or 80M) and a more lightly doped lateral extension (60E or 62E), are formed in the semiconductor body. An anneal is performed during or subsequent to introduction of semiconductor dopant that defines the source/drain zones. The body material is typically provided with at least one more heavily doped halo pocket portion (100 and 102) along the source/drain zones. The vertical dopant profile resulting from the body-material dopants alleviates punchthrough and reduces current leakage.

Abstract translation: 绝缘栅场效应晶体管（110）的制造需要通常将三个体材料掺杂剂（通常通过掩模中的开口）引入半导体主体的主体材料（50）中，以便在三层中达到各自的最大掺杂剂浓度 不同垂直位置的身材。 随后限定栅电极（74），之后在每一个具有主要部分（60M或80M）和更轻掺杂的侧向延伸部（60E或62E）的一对源极/漏极区域（60和62）上形成 半导体体。 在引入定义源极/漏极区的半导体掺杂剂期间或之后进行退火。 主体材料通常沿着源极/漏极区域设置有至少一个更重掺杂的卤素口袋部分（100和102）。 由体材料掺杂物产生的垂直掺杂剂分布减轻穿透并减少电流泄漏。

公开(公告)号：US07785971B1

公开(公告)日：2010-08-31

申请号：US11703350

申请日：2007-02-06

Applicant: Constantin Bulucea ,  Fu-Cheng Wang ,  Prasad Chaparala

Inventor： Constantin Bulucea ,  Fu-Cheng Wang ,  Prasad Chaparala

IPC: H01L21/336

CPC classification number: H01L29/1083 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/105

Abstract: Fabrication of complementary first and second insulated-gate field-effect transistors (110 or 112 and 120 or 122) from a semiconductor body entails separately introducing (i) three body-material dopants into the body material (50) for the first transistor so as to reach respective maximum dopant concentrations at three different locations in the first transistor's body material and (ii) two body-material dopants into the body material (130) for the second transistor so as to reach respective maximum dopant concentrations at two different locations in the second transistor's body material. Gate electrodes (74 or 94 and 154 or 194) are subsequently defined after which source/drain zones (60, 62 or 80, 82 and 140, 142 or 160, 162) are formed in the semiconductor body. The vertical dopant profiles resulting from the body-material dopants alleviate punchthrough and reduce current leakage.

Abstract translation: 从半导体主体制造互补的第一和第二绝缘栅场效应晶体管（110或112和120或122）需要将（i）三个体材料掺杂物分别引入用于第一晶体管的体材料（50）中，以便 以在第一晶体管主体材料中的三个不同位置处达到各自的最大掺杂浓度，和（ii）两个体材料掺杂物进入用于第二晶体管的主体材料（130）中，以便达到第二晶体管的两个不同位置处的各自的最大掺杂浓度 第二晶体管的主体材料。 随后在半导体本体中形成源/漏区（60,62或80,82和140,142或160,162）之后限定栅电极（74或94和154或194）。 由体材料掺杂物产生的垂直掺杂剂分布减轻穿透并减少电流泄漏。

公开(公告)号：US07145191B1

公开(公告)日：2006-12-05

申请号：US10922035

申请日：2004-08-18

Applicant: Chih Sieh Teng ,  Constantin Bulucea ,  Chin-Miin Shyu ,  Fu-Cheng Wang ,  Prasad Chaparala

Inventor： Chih Sieh Teng ,  Constantin Bulucea ,  Chin-Miin Shyu ,  Fu-Cheng Wang ,  Prasad Chaparala

IPC: H01L29/76

CPC classification number: H01L29/1083 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/105

Abstract: The source/drain zones (140 and 142 or 160 and 162) of a p-channel IGFET (120 or 122) are provided with graded-junction characteristics to reduce junction capacitance, thereby increasing switching speed. Each source/drain zone contains a main portion (140M, 142M, 160M, or 162M) and a more lightly doped lower portion (140L, 142L, 160L, or 162L) underlying, and vertically continuous with, the main portion.

Abstract translation: p沟道IGFET（120或122）的源极/漏极区（140和142或160和162）具有渐变结特征以减小结电容，从而提高开关速度。 每个源极/漏极区域包含主要部分（140M，142M，160M，或162M）和较轻掺杂的下部分（140L，142L，160L或162L），并且垂直连续 ，主要部分。

公开(公告)号：US06548842B1

公开(公告)日：2003-04-15

申请号：US09540442

申请日：2000-03-31

Applicant: Constantin Bulucea ,  Fu-Cheng Wang ,  Prasad Chaparala

Inventor： Constantin Bulucea ,  Fu-Cheng Wang ,  Prasad Chaparala

IPC: H01L2994

CPC classification number: H01L29/66492 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823892 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/665

Abstract: An IGFET (40 or 42) has a channel zone (64 or 84) situated in body material (50). Short-channel threshold voltage roll-off and punchthrough are alleviated by arranging for the net dopant concentration in the channel zone to longitudinally reach a local surface minimum at a location between the IGFET's source/drain zones (60 and 62 or 80 and 82) and by arranging for the net dopant concentration in the body material to reach a local subsurface maximum more than 0.1 &mgr;m deep into the body material but not more than 0.4 &mgr;m deep into the body material.

Abstract translation: IGFET（40或42）具有位于主体材料（50）中的通道区（64或84）。 通过设置通道区域中的净掺杂剂浓度以在IGFET的源极/漏极区域（60和62或80和82）之间的位置处纵向达到局部表面最小值来减轻短通道阈值电压滚降和穿透，以及 通过布置主体材料中的净掺杂剂浓度达到主体材料深度超过0.1μm的局部地下最大深度，但不超过0.4μm的主体材料深度。

公开(公告)号：US08395212B2

公开(公告)日：2013-03-12

申请号：US13177552

申请日：2011-07-06

Applicant: Constantin Bulucea

Inventor： Constantin Bulucea

IPC: H01L27/088

CPC classification number: H01L21/823892 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/1203 ,  H01L29/1045 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/7835

Abstract: An insulated-gate field-effect transistor (100, 100V, 140, 150, 150V, 160, 170, 170V, 180, 180V, 190, 210, 210W, 220, 220U, 220V, 220W, 380, or 480) has a hypoabrupt vertical dopant profile below one (104 or 264) of its source/drain zones for reducing the parasitic capacitance along the pn junction between that source/drain zone and adjoining body material (108 or 268). In particular, the concentration of semiconductor dopant which defines the conductivity type of the body material increases by at least a factor of 10 in moving from that source/drain zone down to an underlying body-material location no more than 10 times deeper below the upper semiconductor surface than that source/drain zone. The body material preferably includes a more heavily doped pocket portion (120 or 280) situated along the other source/drain zone (102 or 262). The combination of the hypoabrupt vertical dopant profile below the first-mentioned source/drain zone, normally serving as the drain, and the pocket portion along the second-mentioned source/drain zone, normally serving as the source, enables the resultant asymmetric transistor to be especially suitable for high-speed analog applications.

Abstract translation: 绝缘栅场效应晶体管（100,100V，140,150,150V，160,170,170V，180,180V，190,210,210W，220,220U，220V，220W，380或480）具有 低于其源极/漏极区（104或264）的垂直掺杂剂分布，用于减小源极/漏极区与邻接体材料（108或268）之间的pn结的寄生电容。 特别地，限定主体材料的导电类型的半导体掺杂剂的浓度在从该源极/漏极区向下移动到下面的主体材料位置时不小于10倍深度的上方增加至少10倍 半导体表面比该源/漏区。 主体材料优选地包括沿着另一个源极/漏极区（102或262）设置的更重掺杂的凹穴部分（120或280）。 通常用作漏极的第一提及的源极/漏极区下方的低破坏垂直掺杂物分布以及通常用作源的第二次提供的源极/漏极区的凹穴部分的组合使得所得的不对称晶体管能够 特别适用于高速模拟应用。

公开(公告)号：US08377768B2

公开(公告)日：2013-02-19

申请号：US13293096

申请日：2011-11-09

Applicant: Constantin Bulucea ,  William D. French ,  Donald M. Archer ,  Jeng-Jiun Yang ,  Sandeep R. Bahl ,  D. Courtney Parker

Inventor： Constantin Bulucea ,  William D. French ,  Donald M. Archer ,  Jeng-Jiun Yang ,  Sandeep R. Bahl ,  D. Courtney Parker

IPC: H01L21/8238

CPC classification number: H01L29/1083 ,  H01L21/26513 ,  H01L21/2652 ,  H01L21/26586 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823892 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/518 ,  H01L29/66659 ,  H01L29/7835

Abstract: A group of high-performance like-polarity insulated-gate field-effect transistors (100, 108, 112, 116, 120, and 124 or 102, 110, 114, 118, 122, and 126) have selectably different configurations of lateral source/drain extensions, halo pockets, and gate dielectric thicknesses suitable for a semiconductor fabrication platform that provides a wide variety of transistors for analog and/or digital applications. Each transistor has a pair of source/drain zones, a gate dielectric layer, and a gate electrode. Each source/drain zone includes a main portion and a more lightly doped lateral extension. The lateral extension of one of the source/drain zones of one of the transistors is more heavily doped or/and extends less deeply below the upper semiconductor surface than the lateral extension of one of the source/drain zones of another of the transistors.

Abstract translation: 一组高性能类似极性的绝缘栅场效应晶体管（100,108,112,116,120和124或102,110,114,118,122和126）具有可选择地不同的侧向源 /漏极延伸，光晕口和栅介质厚度，适用于为模拟和/或数字应用提供各种晶体管的半导体制造平台。 每个晶体管具有一对源极/漏极区，栅极介电层和栅电极。 每个源极/漏极区域包括主要部分和更轻掺杂的横向延伸部分。 一个晶体管的一个源极/漏极区域的横向延伸比另一个晶体管的源极/漏极区域之一的横向延伸更深地掺杂或/并且在上部半导体表面之下更深地延伸。

公开(公告)号：US20100244151A1

公开(公告)日：2010-09-30

申请号：US12382974

申请日：2009-03-27

Applicant: William D. French ,  Constantin Bulucea

Inventor： William D. French ,  Constantin Bulucea

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L21/26513 ,  H01L21/2652 ,  H01L21/2658 ,  H01L21/26586 ,  H01L21/28202 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66537 ,  H01L29/66659 ,  H01L29/7835

Abstract: An insulated-gate field-effect transistor (100W) has a source (980) and a drain (242) laterally separated by a channel zone (244) of body material (180) of a semiconductor body. A gate electrode (262) overlies a gate dielectric layer (260) above the channel zone. A more heavily doped pocket portion (250) of the body material normally extends largely along only the source so that the IGFET is an asymmetric device. The source has a main source portion (980M) and a more lightly doped lateral source extension (980E). The semiconductor dopant which defines the source reaches multiple local concentration maxima in defining the source extension. The procedure involved in defining the source extension with semiconductor dopant that reaches two such local concentration maxima enables source/drain extensions of mutually different characteristics for three insulated-gate field-effect transistors to be defined in only two source/drain-extension doping operations.

Abstract translation: 绝缘栅场效应晶体管（100W）具有由半导体主体的主体材料（180）的沟道区（244）横向隔开的源极（980）和漏极（242）。 栅电极（262）覆盖沟道区上方的栅介电层（260）。 主体材料的更重掺杂的袋部分（250）通常沿着源极大部分地延伸，使得IGFET是非对称的装置。 源极具有主源部分（980M）和更轻掺杂的侧向源延伸部（980E）。 限定源极的半导体掺杂剂在限定源延伸时达到多个局部最大浓度。 用半导体掺杂剂定义达到两个这样的局部浓度最大值的源极扩展所涉及的过程使得三个绝缘栅场效应晶体管的源极/漏极扩展能够仅在两个源极/漏极 - 扩展掺杂操作中被定义。

公开(公告)号：US20100244150A1

公开(公告)日：2010-09-30

申请号：US12382972

申请日：2009-03-27

Applicant: Sandeep R. Bahl ,  William D. French ,  Constantin Bulucea

Inventor： Sandeep R. Bahl ,  William D. French ,  Constantin Bulucea

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7835 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/82285 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/0922 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/167 ,  H01L29/6659 ,  H01L29/66659

Abstract: An insulated-gate field-effect transistor (100) provided along an upper surface of a semiconductor body contains a pair of source/drain zones (240 and 242) laterally separated by a channel zone (244). A gate electrode (262) overlies a gate dielectric layer (260) above the channel zone. Each source/drain zone includes a main portion (240M or 242M) and a more lightly doped lateral extension (240E or 242E) laterally continuous with the main portion and extending laterally under the gate electrode. The lateral extensions, which terminate the channel zone along the upper semiconductor surface, are respectively largely defined by a pair of semiconductor dopants of different atomic weights. With the transistor being an asymmetric device, the source/drain zones constitute a source and a drain. The lateral extension of the source is then more lightly doped than, and defined with dopant of higher atomic weight, than the lateral extension of the drain.

Abstract translation: 沿着半导体主体的上表面设置的绝缘栅场效应晶体管（100）包含由沟道区（244）横向隔开的一对源极/漏极区（240和242）。 栅电极（262）覆盖沟道区上方的栅介电层（260）。 每个源极/漏极区域包括与主要部分横向连续并在栅电极下方横向延伸的主要部分（240M或242M）和更轻掺杂的侧向延伸部（240E或242E）。 沿着上半导体表面终止沟道区的横向延伸部分分别由不同原子量的一对半导体掺杂剂限定。 在晶体管是非对称器件的情况下，源极/漏极区域构成源极和漏极。 源极的横向延伸比起漏极的横向延伸稍微掺杂，并且由原子量较高的掺杂剂限定。

公开(公告)号：US07595243B1

公开(公告)日：2009-09-29

申请号：US11495225

申请日：2006-07-28

Applicant: Constantin Bulucea ,  Philipp Lindorfer

Inventor： Constantin Bulucea ,  Philipp Lindorfer

IPC: H01L21/8236

CPC classification number: H01L21/823807 ,  H01L21/26586 ,  H01L27/0883 ,  H01L27/0928 ,  H01L29/1041 ,  H01L29/105 ,  H01L29/665 ,  H01L29/7833

Abstract: A semiconductor technology combines a normally off n-channel channel-junction insulated-gate field-effect transistor (“IGFET”) (104) and an n-channel surface-channel IGFET (100 or 160) to reduce low-frequency 1/f noise. The channel-junction IGFET is normally fabricated to be of materially greater gate dielectric thickness than the surface-channel IGFET so as to operate across a greater voltage range than the surface-channel IGFET. A p-channel surface-channel IGFET (102 or 162), which is typically fabricated to be of approximately the same gate-dielectric thickness as the n-channel surface-channel IGFET, is preferably combined with the two n-channel IGFETs to produce a complementary-IGFET structure. A further p-channel IGFET (106, 180, 184, or 192), which is typically fabricated to be of approximately the same gate dielectric thickness as the n-channel channel-junction IGFET, is also preferably included. The further p-channel IGFET can be a surface-channel or channel-junction device.

Abstract translation: 半导体技术结合了正常n沟道沟道结绝缘栅场效应晶体管（“IGFET”）（104）和n沟道表面沟道IGFET（100或160），以降低低频1 / f 噪声。 沟道结IGFET通常被制造为具有比表面沟道IGFET大得多的栅介质厚度，以便在比表面沟道IGFET更大的电压范围内工作。 典型地制造为与n沟道表面沟道IGFET大致相同的栅介质厚度的p沟道表面沟道IGFET（102或162）优选地与两个n沟道IGFET组合以产生 互补IGFET结构。 还优选包括通常被制造为具有与n沟道沟道结IGFET大致相同的栅介质厚度的另外的p沟道IGFET（106,180,184或192）。 另外的p沟道IGFET可以是表面沟道或沟道结器件。

公开(公告)号：US07081663B2

公开(公告)日：2006-07-25

申请号：US10054653

申请日：2002-01-18

Applicant: Constantin Bulucea

Inventor： Constantin Bulucea

IPC: H01L29/93

CPC classification number: H01L27/0808 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1243

Abstract: A semiconductor junction varactor utilizes gate enhancement for enabling the varactor to achieve a high ratio of maximum capacitance to minimum capacitance. The varactor has a gate region (131 or 181) divided into multiple portions of differing zero-point threshold voltages for enabling the varactor capacitance to vary relatively gradually with a control voltage applied to the varactor.

Abstract translation: 半导体结变容二极管利用栅极增强来使变容二极管实现最大电容与最小电容的高比率。 变容二极管具有被分成不同零点阈值电压的多个部分的栅极区域（131或181），以使变容二极管电容随施加到变容二极管的控制电压相对逐渐变化。