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11.发明授权Echo canceller with short processing delay and decreased multiplication number 失效回波消除器具有短处理延迟和减少的倍数
公开(公告)号：US4951269A
公开(公告)日：1990-08-21
申请号：US216907
申请日：1988-06-24
CPC分类号： H04B3/23 , H03H21/00 , H03H21/0027 , Y10S367/901 , Y10S367/903
摘要： An echo canceller in a system, having a long impulse response such as in an acoustic system, which employs a fast Fourier transform to transform input data represented in the time domain into signals represented in the frequency domain to reduce calculations. To solve the problem of a long delay, the impulse response length is divided into a plurality of blocks. Each block then has a decreased number of samples within each block. Thus, a fast Fourier transform and finite impulse response type digital filtering are effected, so that the processing delay is decreased while the amount of calculations is kept small.
摘要翻译： PCT No.PCT / JP87 / 00833 Sec。 371日期1988年6月24日第 102（e）日期1988年6月24日PCT提交1987年10月29日PCT公布。 第WO88 / 03341号公报 日期：1988年5月5日。在具有诸如在声学系统中的长脉冲响应的系统中的回波消除器，其采用快速傅里叶变换来将在时域中表示的输入数据变换成在频域中表示的信号以减少计算 。 为了解决长延迟的问题，脉冲响应长度被分成多个块。 每个块在每个块内具有减少的采样数。 因此，实现快速傅里叶变换和有限脉冲响应型数字滤波，使得处理延迟减小，同时计算量保持较小。
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12.发明授权
公开(公告)号：US5091955A
公开(公告)日：1992-02-25
申请号：US545499
申请日：1990-06-29
申请人： Kohei Iseda , Kazumi Satoh , Hideaki Kurihara , Fumio Amano , Shigeyuki Unagami , Koji Okazaki
发明人： Kohei Iseda , Kazumi Satoh , Hideaki Kurihara , Fumio Amano , Shigeyuki Unagami , Koji Okazaki
摘要： Disclosed is a voice coding/decoding system having a transmitting part for transmitting a coded signal of an input voice signal at a bit rate lower than a predetermined transmission bit rate and a receiving part for receiving and decoding the coded signal transmitted from the transmission part. To enable the coding and transmitting of an input voice signal in an optimum state without passing through a buffer memory and without having a negative influence on the coder, the transmitting part provides coders for coding the input voice signal and groups of entropy coders. The inputs of the entropy coders in each group are connected to the output of one of the plurality of coders. The transmitting part further provides an evaluation part for evaluating the characteristics of the outputs of the coders and the entropy coders. The evaluation part extracts those entropy coders having output bit rates lower than the transmission bit rate and extracts, from the coders connected to the extracted entropy coders, a coder having the best output characteristic. Then, the evaluation part outputs a selecting signal indicating the combination of the selected coder and an entropy coder from the extracted entropy coders. The transmitting part further provides a selecting part for selecting, in response to the selecting signal, the codeword passed through the combination of the coder and the entropy coder to be transmitted.
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公开(公告)号：US4312075A
公开(公告)日：1982-01-19
申请号：US56641
申请日：1979-07-11
CPC分类号： H04L7/0334 , H04L7/0331
摘要： A timing-phase recovery circuit, which is suitably mounted on a digital LSI, includes a timing phase recovery circuit. The timing-phase recovery circuit includes a first circuit for extracting a digital timing signal from a received input analogue signal, a second circuit for detecting a virtual zero crossing included in the digital timing signal in synchronism with a sampling signal and a third circuit for carrying out a phase shift with respect to the sampling signal in order to tune the timing signal to the frequency of the virtual zero crossings in a very short period of time.
摘要翻译： 适当地安装在数字LSI上的定时相位恢复电路包括定时相位恢复电路。 定时相位恢复电路包括用于从接收到的输入模拟信号中提取数字定时信号的第一电路，用于与采样信号同步地检测包括在数字定时信号中的虚拟过零点的第二电路和用于承载的第三电路 相对于采样信号产生相移，以便在非常短的时间段内将定时信号调谐到虚拟过零点的频率。
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公开(公告)号：US5528687A
公开(公告)日：1996-06-18
申请号：US201336
申请日：1994-02-24
摘要： An echo canceller provided with an expected echo generating unit which generates an expected echo of a transmission signal and a frequency offset correction unit which detects a phase error between an echo in a received signal and an expected echo from the expected echo generating unit and corrects the frequency offset for the expected echo by an offset frequency estimated based on the phase error, wherein use is made of the expected echo after offset correction by the frequency offset correction unit so as to suppress the echo in the received signal, the frequency offset correction unit using the phase error obtained after normalizing the phase error by the magnitude of the echo in the received signal. By this, it is possible to perform frequency offset correction adaptive to the far-end echo characteristics. Further, it is desirable to perform the frequency offset correction after it is confirmed that the rate of change of the output from a subtractor for cancellation of the near-end echo has become almost zero.
摘要翻译： 一种回波消除器，其具有生成发送信号的预期回波的预期回波发生单元和检测接收信号中的回波与来自预期回波发生单元的期望回波之间的相位误差的频偏校正单元， 通过基于相位误差估计出的偏移频率的期望回波的频率偏移，其中使用由偏移校正单元进行偏移校正之后的预期回波，以抑制接收信号中的回波，频率偏移校正单元 使用在相位误差归一化接收信号中的回波幅度之后获得的相位误差。 由此，可以进行适应于远端回波特性的频偏校正。 此外，期望在确认用于消除近端回波的减法器的输出的变化率已经变为几乎为零之后执行频率偏移校正。
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公开(公告)号：US4571733A
公开(公告)日：1986-02-18
申请号：US527573
申请日：1983-08-17
申请人： Takashi Kaku , Shigeyuki Unagami , Masayoshi Inoue
发明人： Takashi Kaku , Shigeyuki Unagami , Masayoshi Inoue
CPC分类号： H04L25/03133
摘要： An automatic equalization device used in a data communication system includes a unit for extracting a single pulse from a training signal sent from a transmitter and initializing a tap coefficient using the extracted single pulse. The automatic equalization device also includes a first equalization circuit and a second equalization circuit. In the first equalization circuit, an auto-correlation series of the signal corresponding to the single pulse is calculated to provide a symmetric single pulse. In the second equalization circuit, an inverse matrix is calculated from the symmetric single pulse using the auto-correlational series of single pulses. By these calculations, the speed of the initial setting of the tap coefficient is increased.
摘要翻译： PCT No.PCT / JP82 / 00479 Sec。 371日期1983年8月17日 102（e）日期1983年8月17日PCT申请日1982年12月28日PCT公布。 公开号WO83 / 02373 日期：1983年7月7日。在数据通信系统中使用的自动均衡装置包括用于从发送器发送的训练信号中提取单个脉冲并使用提取的单个脉冲初始化抽头系数的单元。 自动均衡装置还包括第一均衡电路和第二均衡电路。 在第一均衡电路中，计算与单个脉冲对应的信号的自相关序列，以提供对称的单个脉冲。 在第二均衡电路中，使用单个脉冲的自相关系列从对称单脉冲计算逆矩阵。 通过这些计算，抽头系数的初始设定的速度增加。
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公开(公告)号：US4445224A
公开(公告)日：1984-04-24
申请号：US327730
申请日：1981-12-04
CPC分类号： H04L7/027 , H03L7/0993 , H04L27/2272 , H04L7/02
摘要： The present invention relates to a digital phase locked loop circuit, particularly to a circuit which realizes accurately digital phase locked loop pull-in operation at a high speed with a simplified circuit structure.In the present invention, in order to obtain a phase difference between a single frequency signal and the digital phase locked loop clock signal which is obtained by dividing a specified frequency signal with a dividing counter, the phase difference is obtained in accordance with the signs, absolute values and amplitude ratio of two adjacent sample values. The sample values of said single frequency signal are taken at two points based on said digital phase locked loop clock signal corresponding to a phase difference of .pi./2 radians of said single frequency signal. A fast pull-in of the digital phase locked loop is realized by setting a value corresponding to the obtained phase difference into a dividing counter.
摘要翻译： 数字锁相环电路技术领域本发明涉及一种数字锁相环电路，特别涉及一种以简化的电路结构实现高速数字锁相环引入操作的电路。 在本发明中，为了获得单分频信号与通过用分频计数器分割指定频率信号而获得的数字锁相环时钟信号之间的相位差，根据符号获得相位差， 两个相邻样本值的绝对值和幅度比。 基于对应于所述单频信号的π/ 2弧度的相位差的所述数字锁相环时钟信号，在两个点处获取所述单频信号的采样值。 通过将与获得的相位差对应的值设置为分频计数器来实现数字锁相环的快速拉入。
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公开(公告)号：US4482973A
公开(公告)日：1984-11-13
申请号：US393120
申请日：1982-06-28
CPC分类号： H03G3/3089
摘要： A digital automatic gain control circuit provided with a first AGC loop and a second AGC loop; activated alternately. The first AGC loop is activated when an input signal is initially supplied. The loop produces a certain digital value calculated as an inverse number of the digital level of the input through predetermined digital arithmetic operations utilizing an approximation polynominal. The calculated digital value is then preset in certain portions of the second AGC loop. The second AGC loop starts operating by using said present value, then uses the digital level of the input itself, instead of the preset value, and produces an automatic gain controlled digital output. Utilizing said preset value as an initial input to the second AGC loop allows for rapid stabilization of the automatic gain controlled digital output.
摘要翻译： 一种具有第一AGC环路和第二AGC环路的数字自动增益控制电路; 交替激活。 当最初提供输入信号时，第一个AGC环路被激活。 该循环通过利用近似多项式的预定数字运算产生通过输入的数字电平的倒数计算出的某个数字值。 然后将计算出的数字值预设在第二AGC环路的某些部分。 第二AGC循环通过使用所述当前值开始运行，然后使用输入本身的数字电平而不是预设值，并产生自动增益控制的数字输出。 利用所述预设值作为第二AGC环路的初始输入允许自动增益受控数字输出的快速稳定。
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公开(公告)号：US5159611A
公开(公告)日：1992-10-27
申请号：US860210
申请日：1992-03-27
申请人： Yoshihiro Tomita , Kohei Iseda , Shigeyuki Unagami
发明人： Yoshihiro Tomita , Kohei Iseda , Shigeyuki Unagami
CPC分类号： H04B14/046 , H04N19/154 , H04N19/30 , H04N19/60
摘要： A variable rate coder for transforming an input signal into a low bit rate digital signal, comprising: a plurality of coding units each comprising an output quantizer having a different number of output bits, and each independently transforming the input signal into a respective compressed digital signal. A plurality of bit rate determined circuits are provided to determine an output of one of the plurality of coding units as a candidate output of the coder by a respective individual determining method, in which method, the quality of the signal which is regenerated from the output of each coding unit is compared with an individual predetermined quality evaluating standard, and then the candidate output of the coding unit having the smallest number of output bits, among the candidate outputs of coding units satisfying each standard, is determined as the actual output of the coder. One candidate output, among the plurality of the determined candidate outputs and, which is further determined by a most suitable determining method relative to the level of the input signal, thus is selected as the actual output of the coder. Further, when the number of the output bits in each of the coding units can be variably set, the most suitable number of output bits for the actual output of the coder is calculated based on prediction gains of the coding units, a required signal-to-noise ratio of the coder, and an ADC signal-to-noise ratio at the analog to digital converter, and the number of the output bits in each of the coding units is set based on the above calculated value, before the above operation by the bit rate determining circuits.
摘要翻译： 一种用于将输入信号变换为低比特率数字信号的可变速率编码器，包括：多个编码单元，每个编码单元包括具有不同数目的输出位的输出量化器，并且各自独立地将输入信号变换为相应的压缩数字信号 。 提供多个比特率确定电路，以通过各自的确定方法确定多个编码单元之一的输出作为编码器的候选输出，在该方法中，从输出再生的信号的质量 将每个编码单元与各个预定质量评估标准进行比较，然后确定满足每个标准的编码单元的候选输出中具有最小输出比特数的编码单元的候选输出作为实际输出 编码器 因此，选择多个确定的候选输出中的一个候选输出，并且相对于输入信号的电平进一步由最合适的确定方法确定，作为编码器的实际输出。 此外，当可以可变地设置每个编码单元中的输出比特数时，基于编码单元的预测增益来计算编码器的实际输出的最合适数量的输出比特，所需信号到 编码器的噪声比和模数转换器的ADC信噪比，并且在上述操作之前，基于上述计算值设置每个编码单元中的输出比特数， 比特率确定电路。
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公开(公告)号：US5103481A
公开(公告)日：1992-04-07
申请号：US507658
申请日：1990-04-10
CPC分类号： G10L25/78
摘要： Speech presence versus silence is decided by a discriminator which can use a certain combination of parameter values: signal power, prediction error power, prediction error power deviation, and zero crossings.
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