公开(公告)号：US10957759B2

公开(公告)日：2021-03-23

申请号：US16235486

申请日：2018-12-28

Applicant: General Electric Company

Inventor： Stephen Daley Arthur ,  Reza Ghandi ,  Alexander Viktorovich Bolotnikov ,  David Alan Lilienfeld ,  Peter Almern Losee

IPC: H01L29/06 ,  H01L29/16 ,  H01L21/04 ,  H01L29/66

Abstract: A silicon carbide (SiC) charge balance (CB) device includes a CB layer, which includes a first epitaxial (epi) layer. An active area of the first epi layer includes a first doping concentration of a first conductivity type and a first plurality of CB regions of a second conductivity type. A termination area of the first epi layer includes a minimized epi doping concentration of the first conductivity type. The SiC—CB device also includes a device layer, which includes a second epi layer disposed on the CB layer. An active area of the second epi layer includes the first doping concentration of the first conductivity type. A termination area of the device layer includes the minimized epi doping concentration of the first conductivity type and a first plurality of floating regions of the second conductivity type that form a junction termination of the device.

公开(公告)号：US20190245035A1

公开(公告)日：2019-08-08

申请号：US15890077

申请日：2018-02-06

Applicant: General Electric Company

Inventor： Reza Ghandi ,  David Alan Lilienfeld ,  Alexander Viktorovich Bolotnikov ,  Peter Almern Losee

IPC: H01L29/06 ,  H01L29/16 ,  H01L21/02 ,  H01L21/761 ,  H01L21/265 ,  H01L21/324 ,  H01L27/088 ,  H01L27/092

CPC classification number: H01L29/0646 ,  H01L21/02529 ,  H01L21/26506 ,  H01L21/324 ,  H01L21/761 ,  H01L27/088 ,  H01L27/092 ,  H01L29/1608

Abstract: An integrated circuit includes a silicon carbide (SiC) epitaxial layer disposed on a SiC layer, wherein the SiC epitaxial layer has a first conductivity-type and the SiC layer has a second conductivity-type that is opposite to the first conductivity-type. The integrated circuit also includes a junction isolation feature disposed in the SiC epitaxial layer and having the second conductivity-type. The junction isolation feature extends vertically through a thickness of the SiC epitaxial layer and contacts the SiC layer, and wherein the junction isolation feature has a depth of at least about 2 micrometers (μm).

公开(公告)号：US20190140048A1

公开(公告)日：2019-05-09

申请号：US16010531

申请日：2018-06-18

Applicant: General Electric Company

Inventor： Alexander Viktorovich Bolotnikov ,  Reza Ghandi ,  David Alan Lilienfeld ,  Peter Almern Losee

IPC: H01L29/06 ,  H01L21/04 ,  H01L29/20 ,  H01L21/266 ,  H01L29/78 ,  H01L21/265 ,  H01L29/16

Abstract: The subject matter disclosed herein relates to super-junction (SJ) power devices and, more specifically, to edge termination techniques for SJ power devices. A semiconductor super-junction (SJ) device includes one or more epitaxial (epi) layers having a termination region disposed adjacent to an active region. The termination region includes a plurality of vertical pillars of a first and a second conductivity-type, wherein, moving outward from the active region, a respective width of each successive vertical pillar is the same or smaller. The termination region also includes a plurality of compensated regions having a low doping concentration disposed directly between a first side of each vertical pillar of the first conductivity-type and a first side of each vertical pillar of the second conductivity-type, wherein, moving outward from the active region, a respective width of each successive compensated region is the same or greater.

公开(公告)号：US10243039B2

公开(公告)日：2019-03-26

申请号：US15077579

申请日：2016-03-22

Applicant: General Electric Company

Inventor： Alexander Viktorovich Bolotnikov ,  Peter Almern Losee ,  David Alan Lilienfeld ,  Reza Ghandi

IPC: H01L21/04 ,  H01L29/06 ,  H01L29/16 ,  H01L29/66 ,  H01L29/73 ,  H01L29/78 ,  H01L29/732 ,  H01L29/808 ,  H01L29/861 ,  H01L29/872

Abstract: A super junction (SJ) device may include one or more charge balance (CB) layers. Each CB layer may include an epitaxial (epi) layer having a first conductivity type and a plurality of charge balance (CB) regions having a second conductivity type. Additionally, the SJ device may include a connection region having the second conductivity type that extends from a region disposed in a top surface of a device layer of the SJ device to one or more of the CB regions. The connection region may enable carriers to flow directly from the region to the one or more CB regions, which may decrease switching losses of the SJ device.

公开(公告)号：US20180166531A1

公开(公告)日：2018-06-14

申请号：US15379214

申请日：2016-12-14

Applicant: General Electric Company

Inventor： Alexander Viktorovich Bolotnikov ,  Reza Ghandi ,  David Alan Lilienfeld ,  Peter Almern Losee

IPC: H01L29/06 ,  H01L29/36 ,  H01L29/16 ,  H01L29/20 ,  H01L21/265 ,  H01L21/266

CPC classification number: H01L29/0634 ,  H01L21/26506 ,  H01L21/266 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/36

Abstract: The subject matter disclosed herein relates to super-junction (SJ) power devices and, more specifically, to edge termination techniques for SJ power devices. A semiconductor super-junction (SJ) device includes one or more epitaxial (epi) layers having a termination region disposed adjacent to an active region. The termination region includes a plurality of vertical pillars of a first and a second conductivity-type, wherein, moving outward from the active region, a respective width of each successive vertical pillar is the same or smaller. The termination region also includes a plurality of compensated regions having a low doping concentration disposed directly between a first side of each vertical pillar of the first conductivity-type and a first side of each vertical pillar of the second conductivity-type, wherein, moving outward from the active region, a respective width of each successive compensated region is the same or greater.

公开(公告)号：US12191384B2

公开(公告)日：2025-01-07

申请号：US17338337

申请日：2021-06-03

Applicant: General Electric Company

Inventor： Stephen Daley Arthur ,  Alexander Viktorovich Bolotnikov ,  Reza Ghandi ,  David Alan Lilienfeld ,  Peter Almern Losee

IPC: H01L29/78 ,  H01L21/04 ,  H01L29/08 ,  H01L29/10 ,  H01L29/16 ,  H01L29/66

Abstract: A charge balanced (CB) trench-metal-oxide-semiconductor field-effect transistor (MOSFET) device may include a charge balanced (CB) layer defined within a first epitaxial (epi) layer that has a first conductivity type. The CB layer may include charge balanced (CB) regions that has a second conductivity type. The CB trench-MOSFET device may include a device layer defined in a second epi layer and having the first conductivity type, where the device layer is disposed on the CB layer. The device layer may include a source region, a base region, a trench feature, and a shield region having the second conductivity type disposed at a bottom surface of the trench feature. The device layer may also include a charge balanced (CB) bus region having the second conductivity type that extends between and electrically couples the CB regions of the CB layer to at least one region of the device layer having the second conductivity type.

公开(公告)号：US11764257B2

公开(公告)日：2023-09-19

申请号：US17572274

申请日：2022-01-10

Applicant: General Electric Company

Inventor： Stephen Daley Arthur ,  Victor Mario Torres ,  Michael J. Hartig ,  Reza Ghandi ,  David Alan Lilienfeld ,  Alexander Viktorovich Bolotnikov

IPC: H01L29/15 ,  H01L31/0312 ,  H01L29/06 ,  H01L29/16 ,  H01L21/04 ,  H01L29/66

CPC classification number: H01L29/0634 ,  H01L21/0465 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/1608 ,  H01L29/66068

Abstract: A disclosed super-junction (SJ) device includes a first epitaxial (epi) layer that forms a first SJ layer of the SJ device, and includes a second epi layer disposed on the first SJ layer that forms a device layer of the SJ device. An active area of the first and second epi layers includes a first set of SJ pillars comprising a particular doping concentration of a first conductivity type and a second set of SJ pillars comprising the particular doping concentration of a second conductivity type. A termination area of the first and second epi layers has a minimized epi doping concentration of the first conductivity type that is less than the particular doping concentration, and the termination area of the second epi layer includes a plurality of floating regions of the second conductivity type that form a junction termination of the SJ device.

公开(公告)号：US11417759B2

公开(公告)日：2022-08-16

申请号：US16433809

申请日：2019-06-06

Applicant: General Electric Company

Inventor： Stephen Daley Arthur ,  Joseph Darryl Michael ,  Tammy Lynn Johnson ,  David Alan Lilienfeld ,  Kevin Sean Matocha ,  Jody Alan Fronheiser ,  William Gregg Hawkins

IPC: H01L29/78 ,  H01L21/04 ,  H01L29/45 ,  H01L29/16 ,  H01L29/49 ,  H01L29/739 ,  H01L29/745 ,  H01L23/04 ,  H01L21/50

Abstract: According to one embodiment, a semiconductor device, having a semiconductor substrate comprising silicon carbide with a gate electrode disposed on a portion of the substrate on a first surface with, a drain electrode disposed on a second surface of the substrate. There is a dielectric layer disposed on the gate electrode and a remedial layer disposed about the dielectric layer, wherein the remedial layer is configured to mitigate negative bias temperature instability maintaining a change in threshold voltage of less than about 1 volt. A source electrode is disposed on the remedial layer, wherein the source electrode is electrically coupled to a contact region of the semiconductor substrate.

公开(公告)号：US11056586B2

公开(公告)日：2021-07-06

申请号：US16147216

申请日：2018-09-28

Applicant: General Electric Company

Inventor： Stephen Daley Arthur ,  Alexander Viktorovich Bolotnikov ,  Reza Ghandi ,  David Alan Lilienfeld ,  Peter Almem Losee

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/66 ,  H01L29/16 ,  H01L21/04 ,  H01L29/08

Abstract: A charge balanced (CB) trench-metal-oxide-semiconductor field-effect transistor (MOSFET) device may include a charge balanced (CB) layer defined within a first epitaxial (epi) layer that has a first conductivity type. The CB layer may include charge balanced (CB) regions that has a second conductivity type. The CB trench-MOSFET device may include a device layer defined in a second epi layer and having the first conductivity type, where the device layer is disposed on the CB layer. The device layer may include a source region, a base region, a trench feature, and a shield region having the second conductivity type disposed at a bottom surface of the trench feature. The device layer may also include a charge balanced (CB) bus region having the second conductivity type that extends between and electrically couples the CB regions of the CB layer to at least one region of the device layer having the second conductivity type.

公开(公告)号：US10608079B2

公开(公告)日：2020-03-31

申请号：US15890077

申请日：2018-02-06

Applicant: General Electric Company

Inventor： Reza Ghandi ,  David Alan Lilienfeld ,  Alexander Viktorovich Bolotnikov ,  Peter Almern Losee

IPC: H01L29/06 ,  H01L29/16 ,  H01L21/02 ,  H01L27/092 ,  H01L21/265 ,  H01L21/324 ,  H01L27/088 ,  H01L21/761 ,  H01L21/82 ,  H01L27/06 ,  H01L21/8234

Abstract: An integrated circuit includes a silicon carbide (SiC) epitaxial layer disposed on a SiC layer, wherein the SiC epitaxial layer has a first conductivity-type and the SiC layer has a second conductivity-type that is opposite to the first conductivity-type. The integrated circuit also includes a junction isolation feature disposed in the SiC epitaxial layer and having the second conductivity-type. The junction isolation feature extends vertically through a thickness of the SiC epitaxial layer and contacts the SiC layer, and wherein the junction isolation feature has a depth of at least about 2 micrometers (μm).