公开(公告)号：US20190273132A1

公开(公告)日：2019-09-05

申请号：US15911831

申请日：2018-03-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Michael Zierak ,  Anthony K. Stamper ,  John J. Pekarik ,  Vibhor Jain

IPC: H01L29/06 ,  H01L23/48 ,  H01L21/764 ,  H01L21/762 ,  H01L21/768

Abstract: Structures that include an airgap and methods for forming a structure that includes an airgap. A layer stack is epitaxially grown on a substrate and includes a first semiconductor layer and a second semiconductor layer on a substrate. A plurality of openings are formed that extend through a device region of the first semiconductor layer to the second semiconductor layer. The second semiconductor layer is etched through the openings and selective to the substrate and the first semiconductor layer so as to form an airgap that is arranged in a vertical direction between the substrate and the device region. A device structure is formed in the device region of the first semiconductor layer.

公开(公告)号：US10388728B1

公开(公告)日：2019-08-20

申请号：US15911831

申请日：2018-03-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Michael Zierak ,  Anthony K. Stamper ,  John J. Pekarik ,  Vibhor Jain

IPC: H01L29/06 ,  H01L23/48 ,  H01L21/768 ,  H01L21/762 ,  H01L21/764

Abstract: Structures that include an airgap and methods for forming a structure that includes an airgap. A layer stack is epitaxially grown on a substrate and includes a first semiconductor layer and a second semiconductor layer on a substrate. A plurality of openings are formed that extend through a device region of the first semiconductor layer to the second semiconductor layer. The second semiconductor layer is etched through the openings and selective to the substrate and the first semiconductor layer so as to form an airgap that is arranged in a vertical direction between the substrate and the device region. A device structure is formed in the device region of the first semiconductor layer.

公开(公告)号：US20170278955A1

公开(公告)日：2017-09-28

申请号：US15081443

申请日：2016-03-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Vibhor Jain ,  Renata Camillo-Castillo ,  Qizhi Liu ,  John J. Pekarik ,  Alvin J. Joseph ,  Peter B. Gray

IPC: H01L29/732 ,  H01L21/762 ,  H01L29/08 ,  H01L29/417 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L29/732 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/41708 ,  H01L29/73

Abstract: Device structures for a bipolar junction transistor and methods for fabricating a device structure using a substrate. One or more primary trench isolation regions are formed that surround an active device region of the substrate and a collector contact region of the substrate. A base layer is formed on the active device region and the collector contact region, and the active device region includes a collector. Each primary trench isolation region extends vertically to a first depth into the substrate. A trench is formed laterally located between the base layer and the collector contact region and that extends vertically through the base layer and into the substrate to a second depth that is less than the first depth. A dielectric is formed in the trench to form a secondary trench isolation region. An emitter is formed on the base layer.

公开(公告)号：US11749599B2

公开(公告)日：2023-09-05

申请号：US17097432

申请日：2020-11-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： John J. Pekarik ,  Anthony K. Stamper ,  Vibhor Jain

IPC: H01L23/52 ,  H01L23/525 ,  H01L21/768 ,  H01L23/00 ,  H01L23/62

CPC classification number: H01L23/5258 ,  H01L21/76843 ,  H01L23/573 ,  H01L23/62 ,  H01L24/16

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to dual thickness fuse structures and methods of manufacture. The structure includes a continuous wiring structure on a single wiring level and composed of conductive material having a fuse portion and a thicker wiring structure.

公开(公告)号：US10971597B2

公开(公告)日：2021-04-06

申请号：US16551061

申请日：2019-08-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Qizhi Liu ,  Vibhor Jain ,  John J. Pekarik

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L21/02 ,  H01L29/165 ,  H01L29/737

Abstract: Device structures and fabrication methods for a bipolar junction transistor. A trench isolation region surrounds an active region that includes a collector. A base layer includes a first section and a second section that are located over the active region. An emitter is positioned on the first section of the base layer, and an extrinsic base layer is positioned on the second section of the base layer. The extrinsic base layer has a side surface adjacent to the emitter. The side surface of the extrinsic base layer is inclined relative to a top surface of the base layer in a direction away from the emitter.

公开(公告)号：US10777668B2

公开(公告)日：2020-09-15

申请号：US16106344

申请日：2018-08-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vibhor Jain ,  John J. Pekarik ,  Qizhi Liu ,  Pernell Dongmo

IPC: H01L29/732 ,  H01L29/08 ,  H01L29/06

Abstract: Device structures and fabrication methods for a bipolar junction transistor. A trench isolation region surrounds an active region that includes a collector. A base layer is arranged over the active region, and a semiconductor layer is arranged on the base layer. The semiconductor layer includes a stepped profile with a first section having a first width adjacent to the base layer and a second section having a second width that is less than the first width. An emitter is arranged on the second section of the semiconductor layer.

公开(公告)号：US10509244B1

公开(公告)日：2019-12-17

申请号：US16216027

申请日：2018-12-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven M. Shank ,  Anthony K. Stamper ,  John J. Ellis-Monaghan ,  Vibhor Jain ,  John J. Pekarik

IPC: G02F1/01

Abstract: Structures for an optical switch, structures for an optical router, and methods of fabricating a structure for an optical switch. A phase change layer is arranged proximate to a waveguide core, and a heater is formed proximate to the phase change layer. The phase change layer is composed of a phase change material having a first state with a first refractive index at a first temperature and a second state with a second refractive index at a second temperature. The heater is configured to selectively transfer heat to the phase change layer for transitioning between the first state and the second state.

公开(公告)号：US10170553B2

公开(公告)日：2019-01-01

申请号：US15626241

申请日：2017-06-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Renata Camillo-Castillo ,  Qizhi Liu ,  John J. Pekarik

IPC: H01L29/423 ,  H01L29/732 ,  H01L21/306 ,  H01L29/08 ,  H01L29/66 ,  H01L29/737 ,  H01L29/06 ,  H01L29/10

Abstract: Device structure and fabrication methods for a bipolar junction transistor. An emitter layer is formed on a base layer and etched to form an emitter of the device structure. The emitter layer has a concentration of an element that varies as a function of the thickness of the emitter layer. The etch rate of the emitter layer varies as a function of the concentration of the element such that the emitter has a variable width over the thickness of the emitter layer.

公开(公告)号：US20180240897A1

公开(公告)日：2018-08-23

申请号：US15437168

申请日：2017-02-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Qizhi Liu ,  Vibhor Jain ,  John J. Pekarik

IPC: H01L29/737 ,  H01L29/10 ,  H01L29/08 ,  H01L29/66 ,  H01L21/306 ,  H01L21/265 ,  H01L29/165

CPC classification number: H01L29/7375 ,  H01L29/165 ,  H01L29/66242

Abstract: Device structures and fabrication methods for a heterojunction bipolar transistor. A collector of the device structure has a top surface and a sidewall that is inclined relative to the top surface. The device structure further includes an emitter, an intrinsic base that has a first thickness, and an extrinsic base coupled with the intrinsic base. The extrinsic base has a lateral arrangement relative to the intrinsic base and relative to the emitter. The intrinsic base has a vertical arrangement between the emitter and the top surface of the collector. The sidewall of the collector extends laterally to undercut the extrinsic base. The extrinsic base has a second thickness that is greater than a first thickness of the intrinsic base.

公开(公告)号：US20180145088A1

公开(公告)日：2018-05-24

申请号：US15355231

申请日：2016-11-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven M. Shank ,  Mark D. Jaffe ,  John J. Pekarik

IPC: H01L27/12 ,  H01L29/06 ,  H01L23/528 ,  H01L21/84 ,  H01L21/8234 ,  H01L21/762 ,  H01L21/768 ,  H01L21/265 ,  H01L29/66

CPC classification number: H01L27/1203 ,  H01L21/265 ,  H01L21/76224 ,  H01L21/76838 ,  H01L21/823481 ,  H01L21/84 ,  H01L23/5283 ,  H01L27/0629 ,  H01L28/20 ,  H01L29/0649 ,  H01L29/66477

Abstract: Device structures for a field-effect transistor with a body contact and methods of forming such device structures. An opening is formed that extends through a device layer of a silicon-on-insulator (SOI) substrate and into a buried oxide layer of the silicon-on-insulator substrate. The buried oxide layer is laterally etched at the location of the opening to define a cavity in the buried oxide layer. The cavity is located partially beneath a section of the device layer, and the cavity is filled with a semiconductor material to form a body contact. A well is formed in the section of the device layer, and the body contact is coupled with a portion of the well.