公开(公告)号：US20140258960A1

公开(公告)日：2014-09-11

申请号：US13792946

申请日：2013-03-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Navneet Jain ,  Yunfei Deng ,  Mahbub Rashed ,  David Doman ,  Qi Xiang ,  Jongwook Kye

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  Y02T10/82

Abstract: An approach and apparatus are provided for optimizing and combining different semiconductor technologies into a single graphic data system. Embodiments include generating a planar semiconductor layout design, generating a three-dimensional (e.g., FinFET) semiconductor layout design, and combining the planar design and the FinFET design in a common graphic data system.

Abstract translation: 提供了将不同半导体技术优化并组合成单个图形数据系统的方法和装置。 实施例包括生成平面半导体布局设计，产生三维（例如，FinFET）半导体布局设计，以及将平面设计和FinFET设计组合在通用图形数据系统中。

公开(公告)号：US20190333853A1

公开(公告)日：2019-10-31

申请号：US16411237

申请日：2019-05-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Juhan Kim ,  Mahbub Rashed ,  Navneet Jain

IPC: H01L23/528 ,  H01L23/50 ,  G06F17/50 ,  H01L23/522 ,  H01L27/02

Abstract: In an exemplary structure, a first conductor connects a power source to integrated circuit devices. The first conductor includes a first axis defining a first side and a second side. A second conductor, perpendicular to the first conductor, is connected to the first conductor by first vias. A third conductor, parallel to the first conductor, is connected to the second conductor by second vias. The third conductor includes a second axis defining a third side and a fourth side. The first side and the third side are aligned in a first plane perpendicular to the conductors and the second side and the fourth side are aligned in a second plane perpendicular to the conductors. The first vias contact the first conductor in only the first side. The second vias contact the third conductor in only the third side. And the second conductor is outside the second plane.

公开(公告)号：US10360334B2

公开(公告)日：2019-07-23

申请号：US15428449

申请日：2017-02-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Navneet Jain ,  Mahbub Rashed ,  Juhan Kim

IPC: G06F17/50

Abstract: Methods and systems assign an alignment context to each of the cells within an integrated circuit layout, from previously established alignment contexts, based on how the different cell widths cause each of the cells to align with adjoining cells. Also, such methods and systems retrieve standard signal delay times for each of the cells from a standard cell library. This allows these methods and systems to adjust the signal delay times for each of the cells based on which alignment context has been assigned to each of the cells, to produce adjusted delay times for each of the cells. Following this, the methods and systems perform a timing analysis of the layout using the adjusted delay times for each of the cells, and output the results of the timing analysis.

公开(公告)号：US10333497B1

公开(公告)日：2019-06-25

申请号：US15944813

申请日：2018-04-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anil Kumar ,  Mahbub Rashed ,  Sushama Davar ,  Navneet Jain

IPC: H03K3/011 ,  G06F13/10 ,  H03K5/24

Abstract: A calibration circuit is connected to an input/output driver, a voltage bias generator is connected to the calibration circuit and the input/output driver, and a temperature sensor is connected to the voltage bias generator. The calibration circuit and input/output driver each include a bank of resistors and corresponding switches. Bodies of the switches are connected to the voltage bias generator, and the switches are biased by a bias signal output from the voltage bias generator. The calibration circuit includes a comparator device connected to the switches and to a reference resistor. Activation and deactivation of selected ones of the switches is made to match the reference resistor. Also, the voltage bias generator adjusts the bias signal when a temperature change is sensed by the temperature sensor. Thus, the switches change current flow as the bias signal changes, without changing which of the switches are activated or deactivated.

公开(公告)号：US10303196B1

公开(公告)日：2019-05-28

申请号：US15966300

申请日：2018-04-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： Navneet Jain ,  Arif A. Siddiqi ,  Mahbub Rashed

IPC: G05F3/20 ,  G11C5/14 ,  H03K19/00 ,  H01L29/78 ,  H01L29/06 ,  H01L27/092

Abstract: Disclosed is a voltage generator that includes a first voltage generation circuit and a second voltage generation circuit. The first voltage generation circuit is selectively operable in a single trimming mode enabling positive trimming only or in a dual trimming mode that shifts the voltage range downward enabling a somewhat smaller amount of positive trimming and also some negative trimming. The second voltage generation circuit is selectively operable in a single trimming mode enabling negative trimming only or in a dual trimming mode that shifts the voltage range upward enabling a somewhat smaller amount of negative trimming and also some positive trimming. Also disclosed is an integrated circuit (IC) chip that incorporates one or more such voltage generators for back-biasing the field effect transistors in one or more circuit blocks, respectively.

公开(公告)号：US10096595B2

公开(公告)日：2018-10-09

申请号：US15286196

申请日：2016-10-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： Juhan Kim ,  Mahbub Rashed ,  Navneet Jain ,  Anurag Mittal ,  Sangmoon Kim

IPC: H01L27/02 ,  H01L27/06 ,  G06F17/50 ,  H01L27/11 ,  H01L29/66

Abstract: At least one method, apparatus and system disclosed involves an antenna diode design for a semiconductor device. A first common diode operatively coupled to a ground node and to a p-well layer serving as an isolated p-well that is formed over a deep n-well that is adjacent to an n-well in a semiconductor device is provided. A first antenna diode formed on the isolated p-well operatively coupled to the p-well layer and operatively coupled to a first signal line of the semiconductor device is provided for discharging accumulated charges on the first signal line. A second antenna diode formed on the isolated p-well operatively coupled to the p-well layer and operatively coupled to a second signal line of semiconductor device is provided for discharging accumulated charges on the second signal line.

公开(公告)号：US20180225406A1

公开(公告)日：2018-08-09

申请号：US15428449

申请日：2017-02-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Navneet Jain ,  Mahbub Rashed ,  Juhan Kim

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5077 ,  G06F2217/84

Abstract: Methods and systems assign an alignment context to each of the cells within an integrated circuit layout, from previously established alignment contexts, based on how the different cell widths cause each of the cells to align with adjoining cells. Also, such methods and systems retrieve standard signal delay times for each of the cells from a standard cell library. This allows these methods and systems to adjust the signal delay times for each of the cells based on which alignment context has been assigned to each of the cells, to produce adjusted delay times for each of the cells. Following this, the methods and systems perform a timing analysis of the layout using the adjusted delay times for each of the cells, and output the results of the timing analysis.

公开(公告)号：US09479179B2

公开(公告)日：2016-10-25

申请号：US14263329

申请日：2014-04-28

Applicant: Globalfoundries Inc.

Inventor： Andy T. Nguyen ,  Navneet Jain

IPC: G01R31/02 ,  H03K23/50 ,  H03K5/22 ,  G01R31/317

CPC classification number: H03K23/50 ,  G01R31/31727 ,  H03K5/22

Abstract: Methodologies and an apparatus for measuring setup and hold times of fabricated semiconductor devices are provided. Embodiments include: providing a first digital frequency divider having an input and an output, the input of the first digital frequency divider receiving a first signal indicating an oscillating signal with a first delay; providing a second digital frequency divider having an input and output, the input of the second digital frequency divider receiving a second signal indicating the oscillating signal with a second delay; and providing a flip-flop having an input and an output, wherein the input of the flip-flop is coupled to the output of the second digital frequency divider and a data signal and clock signal for measuring a set-up time or hold time of a device under test are generated.

Abstract translation: 提供了用于测量制造的半导体器件的建立和保持时间的方法和装置。 实施例包括：提供具有输入和输出的第一数字分频器，第一数字分频器的输入接收指示具有第一延迟的振荡信号的第一信号; 提供具有输入和输出的第二数字分频器，所述第二数字分频器的输入端以第二延迟接收指示所述振荡信号的第二信号; 以及提供具有输入和输出的触发器，其中所述触发器的输入耦合到所述第二数字分频器的输出，以及数据信号和时钟信号，用于测量所述触发器的建立时间或保持时间 生成被测设备。

公开(公告)号：US08904324B2

公开(公告)日：2014-12-02

申请号：US13836057

申请日：2013-03-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Navneet Jain ,  Paul D. Mesa ,  Qinglei Wang ,  Qi Xiang ,  Mahbub Rashed

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  G06F17/505 ,  H01L29/66795

Abstract: A parameterized cell for planar and finFET designs is provided. A parameterized cell (Pcell) describing a planar design is integrated with fin-based design criteria, including fin pitch. For material regions in a planar design that have a corresponding region in a fin design, a quantized value based on the fin pitch is computed. The material can include regions such as active area silicon, contact regions, and local interconnect regions.

Abstract translation: 提供了用于平面和finFET设计的参数化单元。 描述平面设计的参数化单元（Pcell）集成了基于翅片的设计标准，包括翅片间距。 对于在翅片设计中具有对应区域的平面设计中的材料区域，计算基于翅片间距的量化值。 该材料可以包括诸如有源区硅，接触区域和局部互连区域的区域。

公开(公告)号：US20140282323A1

公开(公告)日：2014-09-18

申请号：US13836057

申请日：2013-03-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Navneet Jain ,  Paul D. Mesa ,  Qinglei Wang ,  Qi Xiang ,  Mahbub Rashed

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  G06F17/505 ,  H01L29/66795

Abstract: A parameterized cell for planar and finFET designs is provided. A parameterized cell (Pcell) describing a planar design is integrated with fin-based design criteria, including fin pitch. For material regions in a planar design that have a corresponding region in a fin design, a quantized value based on the fin pitch is computed. The material can include regions such as active area silicon, contact regions, and local interconnect regions.

Abstract translation: 提供了用于平面和finFET设计的参数化单元。 描述平面设计的参数化单元（Pcell）集成了基于翅片的设计标准，包括翅片间距。 对于在翅片设计中具有对应区域的平面设计中的材料区域，计算基于翅片间距的量化值。 该材料可以包括诸如有源区硅，接触区域和局部互连区域的区域。