公开(公告)号：US10431663B2

公开(公告)日：2019-10-01

申请号：US15867036

申请日：2018-01-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Balasubramanian Pranatharthiharan ,  Pietro Montanini ,  Julien Frougier

IPC: H01L27/12 ,  H01L29/423 ,  H01L27/02 ,  H01L29/66 ,  H01L21/306 ,  H01L21/762 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/78 ,  H01L29/10 ,  H01L29/08 ,  H01L27/088

Abstract: Disclosed are methods for forming an integrated circuit with a nanowire-type field effect transistor and the resulting structure. A sacrificial gate is formed on a multi-layer fin. A sidewall spacer is formed with a gate section on the sacrificial gate and fin sections on exposed portions of the fin. Before or after removal of the exposed portions of the fin, the fins sections of the sidewall spacer are removed or reduced in size without exposing the sacrificial gate. Thus, the areas within which epitaxial source/drain regions are to be formed will not be bound by sidewall spacers. Furthermore, isolation material, which is deposited into these areas prior to epitaxial source/drain region formation and which is used to form isolation elements between the transistor gate and source/drain regions, can be removed without removing the isolation elements. Techniques are also disclosed for simultaneous formation of a nanosheet-type and/or fin-type field effect transistors.

公开(公告)号：US10366931B2

公开(公告)日：2019-07-30

申请号：US16133850

申请日：2018-09-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Cheng Chi ,  Pietro Montanini ,  Tenko Yamashita ,  Nicolas Loubet

IPC: H01L29/76 ,  H01L21/8238 ,  H01L27/092

Abstract: This disclosure relates to a method of forming nanosheet devices including: forming a first and second nanosheet stack on a substrate, the first and the second nanosheet stacks including a plurality of vertically spaced nanosheets disposed on the substrate and separated by a plurality of spacing members, each of the plurality of spacing members including a sacrificial layer and a pair of inner spacers formed on lateral ends of the sacrificial layer; growing a pair of epitaxial regions adjacent to the first and second nanosheet stacks from each of the plurality of nanosheets such that each of the plurality of inner spacers is enveloped by one of the epitaxial regions; covering the first nanosheet stack with a mask; and forming a pair of p-type source/drain regions on the second nanosheet stack, each of the pair of p-type source/drain regions being adjacent to the epitaxial regions on the second nanosheet stack.

公开(公告)号：US20190214473A1

公开(公告)日：2019-07-11

申请号：US15867036

申请日：2018-01-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Balasubramanian Pranatharthiharan ,  Pietro Montanini ,  Julien Frougier

IPC: H01L29/423 ,  H01L29/66 ,  H01L21/306 ,  H01L21/762 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/78 ,  H01L29/10 ,  H01L29/08 ,  H01L27/088 ,  H01L27/02

CPC classification number: H01L29/42392 ,  H01L21/30604 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/76224 ,  H01L21/76897 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0207 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7851

Abstract: Disclosed are methods for forming an integrated circuit with a nanowire-type field effect transistor and the resulting structure. A sacrificial gate is formed on a multi-layer fin. A sidewall spacer is formed with a gate section on the sacrificial gate and fin sections on exposed portions of the fin. Before or after removal of the exposed portions of the fin, the fins sections of the sidewall spacer are removed or reduced in size without exposing the sacrificial gate. Thus, the areas within which epitaxial source/drain regions are to be formed will not be bound by sidewall spacers. Furthermore, isolation material, which is deposited into these areas prior to epitaxial source/drain region formation and which is used to form isolation elements between the transistor gate and source/drain regions, can be removed without removing the isolation elements. Techniques are also disclosed for simultaneous formation of a nanosheet-type and/or fin-type field effect transistors.

公开(公告)号：US08987827B2

公开(公告)日：2015-03-24

申请号：US13907690

申请日：2013-05-31

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Pietro Montanini ,  Raymond Joy ,  Marta Mottura ,  Henry K. Utomo

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66636 ,  H01L21/28123 ,  H01L21/76232 ,  H01L29/165 ,  H01L29/7848

Abstract: A method for fabricating enhanced-mobility pFET devices having channel lengths below 50 nm. Gates for pFETs may be patterned in dense arrays on a semiconductor substrate that includes shallow trench isolation (STI) structures. Partially-enclosed voids in the semiconductor substrate may be formed at source and drain regions for the gates, and subsequently filled with epitaxially-grown semiconductor that compressively stresses channel regions below the gates. Some of the gates (dummy gates) may extend over edges of the STI structures to prevent undesirable faceting of the epitaxial material in the source and drain regions.

Abstract translation: 一种制造通道长度低于50nm的增强型迁移率pFET器件的方法。 用于pFET的栅极可以在包括浅沟槽隔离（STI）结构的半导体衬底上以致密阵列图案化。 可以在用于栅极的源极和漏极区域处形成半导体衬底中的部分封闭的空隙，并且随后填充压缩地压缩栅极下方的沟道区域的外延生长的半导体。 一些栅极（伪栅极）可以在STI结构的边缘上延伸，以防止在源极和漏极区域中的外延材料的不期望的刻痕。