公开(公告)号：US20200152765A1

公开(公告)日：2020-05-14

申请号：US16743293

申请日：2020-01-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC. ,  STMicroelectronics, Inc.

Inventor： XIUYU CAI ,  CHUN-CHEN YEH ,  QING LIU ,  RUILONG XIE

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/165 ,  H01L29/161 ,  H01L29/08 ,  H01L21/768 ,  H01L29/417 ,  H01L29/06

Abstract: A semiconductor device that a fin structure, and a gate structure present on a channel region of the fin structure. A composite spacer is present on a sidewall of the gate structure including an upper portion having a first dielectric constant, a lower portion having a second dielectric constant that is less than the first dielectric constant, and an etch barrier layer between sidewalls of the first and second portion of the composite spacer and the gate structure. The etch barrier layer may include an alloy including at least one of silicon, boron and carbon.

公开(公告)号：US20180358452A1

公开(公告)日：2018-12-13

申请号：US15615925

申请日：2017-06-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： YI QI ,  JIANWEI PENG ,  HSIEN-CHING LO ,  RUILONG XIE ,  XUNYUAN ZHANG ,  HUI ZANG

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/78

CPC classification number: H01L29/66666 ,  H01L29/0847 ,  H01L29/6653 ,  H01L29/66787 ,  H01L29/7827

Abstract: Disclosed are embodiments of an improved method for forming a vertical field effect transistor (VFET). In each of the embodiments of the method, a semiconductor fin is formed sufficiently thick (i.e., wide) so that the surface area of the top of the semiconductor fin is sufficiently large to facilitate epitaxial growth thereon of a semiconductor material for a second source/drain region. As a result, the second source/drain region will be sufficiently large to avoid potential contact-related defects (e.g., unlanded contacts, complete silicidation of second source/drain region during contact formation, etc.). Additionally, either before or after this second source/drain region is formed, at least the center portion of the semiconductor fin, which will include the channel region of the VFET, is thinned down to a desired critical dimension for optimal VFET performance. Also disclosed are VFET structure embodiments resulting from this method.

公开(公告)号：US20170200812A1

公开(公告)日：2017-07-13

申请号：US15472556

申请日：2017-03-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES, Inc. ,  STMICROELECTRONICS, INC.

Inventor： XIUYU CAI ,  QING LIU ,  KEJIA WANG ,  RUILONG XIE ,  CHUN-CHEN YEH

IPC: H01L29/66 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/06

CPC classification number: H01L29/66795 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/6656

Abstract: A method for making a semiconductor device may include forming first and second spaced apart semiconductor active regions with an insulating region therebetween, forming at least one sacrificial gate line extending between the first and second spaced apart semiconductor active regions and over the insulating region, and forming sidewall spacers on opposing sides of the at least one sacrificial gate line. The method may further include removing portions of the at least one sacrificial gate line within the sidewall spacers and above the insulating region defining at least one gate line end recess, filling the at least one gate line end recess with a dielectric material, and forming respective replacement gates in place of portions of the at least one sacrificial gate line above the first and second spaced apart semiconductor active regions.

公开(公告)号：US20170103917A1

公开(公告)日：2017-04-13

申请号：US15222261

申请日：2016-07-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC. ,  STMicroelectronics, Inc.

Inventor： XIUYU CAI ,  CHUN-CHEN YEH ,  QING LIU ,  RUILONG XIE

IPC: H01L21/768 ,  H01L29/08 ,  H01L23/535 ,  H01L29/16 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78 ,  H01L29/161

Abstract: A semiconductor device that a fin structure, and a gate structure present on a channel region of the fin structure. A composite spacer is present on a sidewall of the gate structure including an upper portion having a first dielectric constant, a lower portion having a second dielectric constant that is less than the first dielectric constant, and an etch barrier layer between sidewalls of the first and second portion of the composite spacer and the gate structure. The etch barrier layer may include an alloy including at least one of silicon, boron and carbon.

公开(公告)号：US20150333155A1

公开(公告)日：2015-11-19

申请号：US14281021

申请日：2014-05-19

Applicant: STMICROELECTRONICS, INC. ,  GLOBALFOUNDRIES INC ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qing LIU ,  RUILONG XIE ,  XIUYU CAI ,  CHUN-CHEN YEH ,  KEJIA WANG

IPC: H01L29/66 ,  H01L27/088

CPC classification number: H01L29/66795 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/6656

Abstract: A method for making a semiconductor device may include forming first and second spaced apart semiconductor active regions with an insulating region therebetween, forming at least one sacrificial gate line extending between the first and second spaced apart semiconductor active regions and over the insulating region, and forming sidewall spacers on opposing sides of the at least one sacrificial gate line. The method may further include removing portions of the at least one sacrificial gate line within the sidewall spacers and above the insulating region defining at least one gate line end recess, filling the at least one gate line end recess with a dielectric material, and forming respective replacement gates in place of portions of the at least one sacrificial gate line above the first and second spaced apart semiconductor active regions.

Abstract translation: 制造半导体器件的方法可以包括：形成第一和第二间隔开的半导体有源区域，其间具有绝缘区域，形成在第一和第二间隔开的半导体有源区域之间并在绝缘区域上延伸的至少一个牺牲栅极线，以及形成 在所述至少一个牺牲栅极线的相对侧上的侧壁间隔物。 该方法还可以包括去除侧壁间隔物内的至少一个牺牲栅极线的部分，并且在绝缘区域的上方限定限定至少一个栅极端部凹部的部分，用电介质材料填充至少一个栅极端部凹部，并且形成相应的 替代栅极代替在第一和第二间隔开的半导体有源区之上的至少一个牺牲栅极线的部分。