公开(公告)号：US10049942B2

公开(公告)日：2018-08-14

申请号：US14853373

申请日：2015-09-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Anthony I. Chou ,  Judson R. Holt ,  Arvind Kumar ,  Henry K. Utomo

IPC: H01L21/265 ,  H01L21/266 ,  H01L29/167 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L27/092

Abstract: An aspect of the disclosure provides for an asymmetric semiconductor device. The asymmetric semiconductor device may comprise: a substrate; and a fin-shaped field effect transistor (FINFET) disposed on the substrate, the FINFET including: a set of fins disposed proximate a gate; a first epitaxial region disposed on a source region on the set of fins, the first epitaxial region having a first height; and a second epitaxial region disposed on a drain region on the set of fins, the second epitaxial region having a second height, wherein the first height is distinct from the second height.

公开(公告)号：US20170179257A1

公开(公告)日：2017-06-22

申请号：US15453939

申请日：2017-03-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Anthony I. Chou ,  Judson R. Holt ,  Arvind Kumar ,  Henry K. Utomo

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/08 ,  H01L21/306 ,  H01L29/165 ,  H01L21/84 ,  H01L29/10

CPC classification number: H01L29/66636 ,  H01L21/30604 ,  H01L21/84 ,  H01L29/0649 ,  H01L29/0688 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66742 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/786

Abstract: The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a partially depleted semiconductor-on-insulator (SOI) junction isolation structure using a nonuniform trench shape formed by reactive ion etching (RIE) and crystallographic wet etching. The nonuniform trench shape may reduce back channel leakage by providing an effective channel directly below a gate stack having a width that is less than a width of an effective back channel directly above the isolation layer.

公开(公告)号：US20160379999A1

公开(公告)日：2016-12-29

申请号：US14748355

申请日：2015-06-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anthony I. Chou ,  Sungjae Lee ,  Joseph M. Lukaitis ,  Robert R. Robison

IPC: H01L27/12 ,  H01L21/3205 ,  H01L21/22 ,  H01L23/522 ,  H01L23/373

CPC classification number: H01L27/1207 ,  H01L23/3677 ,  H01L23/485 ,  H01L23/5222 ,  H01L23/5228 ,  H01L23/535

Abstract: Methods and structures for capacitively isolating a heat shield from a handle wafer of a silicon-on-insulator substrate. A contact plug is located in a trench extending through a trench isolation region in a device layer of the silicon-on-insulator substrate and at least partially through a buried insulator layer of the silicon-on-insulator substrate. The heat shield is located in an interconnect structure, which also includes a wire coupling the heat shield with the contact plug. An isolation structure is positioned between the contact plug and a portion of the handle wafer. The isolation structure provides the capacitive isolation.

Abstract translation: 将隔热层与绝缘体上硅衬底的处理晶片电容性隔离的方法和结构。 接触插塞位于延伸穿过绝缘体上硅衬底的器件层中的沟槽隔离区域并且至少部分地穿过绝缘体上硅衬底的掩埋绝缘体层的沟槽中。 隔热罩位于互连结构中，其还包括将隔热罩与接触插头连接的线。 隔离结构位于接触塞和处理晶片的一部分之间。 隔离结构提供电容隔离。

公开(公告)号：US09530798B1

公开(公告)日：2016-12-27

申请号：US14748355

申请日：2015-06-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anthony I. Chou ,  Sungjae Lee ,  Joseph M. Lukaitis ,  Robert R. Robison

IPC: H01L23/552 ,  H01L23/66 ,  H01L27/12 ,  H01L23/522 ,  H01L23/373 ,  H01L21/22 ,  H01L21/3205

CPC classification number: H01L27/1207 ,  H01L23/3677 ,  H01L23/485 ,  H01L23/5222 ,  H01L23/5228 ,  H01L23/535

Abstract: Methods and structures for capacitively isolating a heat shield from a handle wafer of a silicon-on-insulator substrate. A contact plug is located in a trench extending through a trench isolation region in a device layer of the silicon-on-insulator substrate and at least partially through a buried insulator layer of the silicon-on-insulator substrate. The heat shield is located in an interconnect structure, which also includes a wire coupling the heat shield with the contact plug. An isolation structure is positioned between the contact plug and a portion of the handle wafer. The isolation structure provides the capacitive isolation.

Abstract translation: 将隔热层与绝缘体上硅衬底的处理晶片电容性隔离的方法和结构。 接触插塞位于延伸穿过绝缘体上硅衬底的器件层中的沟槽隔离区域并且至少部分地穿过绝缘体上硅衬底的掩埋绝缘体层的沟槽中。 隔热罩位于互连结构中，其还包括将隔热罩与接触插头连接的线。 隔离结构位于接触塞和处理晶片的一部分之间。 隔离结构提供电容隔离。