公开(公告)号：US10256152B2

公开(公告)日：2019-04-09

申请号：US15657373

申请日：2017-07-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Qun Gao ,  Naved Siddiqui ,  Anthony I. Chou

IPC: H01L21/76 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L29/51 ,  H01L29/10 ,  H01L29/417 ,  H01L27/092 ,  H01L27/088 ,  H01L27/12 ,  H01L21/762 ,  H01L21/8238

Abstract: One illustrative method disclosed herein includes, among other things, forming a conformal piezoelectric material liner layer on at least the opposing lateral sidewalls of a fin, forming a recessed layer of insulating material on opposite sides of the fin and on the conformal piezoelectric material liner layer, removing portions of the conformal piezoelectric material liner layer positioned above the recessed layer of insulating material to thereby expose a portion of the fin above the recessed upper surface, and forming a gate structure above the recessed layer of insulating material and around a portion of the fin positioned above the recessed upper surface.

公开(公告)号：US20190027601A1

公开(公告)日：2019-01-24

申请号：US15657373

申请日：2017-07-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Qun Gao ,  Naved Siddiqui ,  Anthony I. Chou

IPC: H01L29/78 ,  H01L29/66

Abstract: One illustrative method disclosed herein includes, among other things, forming a conformal piezoelectric material liner layer on at least the opposing lateral sidewalls of a fin, forming a recessed layer of insulating material on opposite sides of the fin and on the conformal piezoelectric material liner layer, removing portions of the conformal piezoelectric material liner layer positioned above the recessed layer of insulating material to thereby expose a portion of the fin above the recessed upper surface, and forming a gate structure above the recessed layer of insulating material and around a portion of the fin positioned above the recessed upper surface.

公开(公告)号：US09484246B2

公开(公告)日：2016-11-01

申请号：US14307604

申请日：2014-06-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anthony I. Chou ,  Arvind Kumar ,  Sungjae Lee ,  Richard A. Wachnik

IPC: H01L21/20 ,  H01L21/762 ,  H01L21/84 ,  H01L21/74 ,  H01L27/12

CPC classification number: H01L21/76283 ,  H01L21/743 ,  H01L21/84 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A buried conductive layer is formed underneath a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. A deep isolation trench laterally surrounding a portion of the buried conductive layer is formed, and is filled with at least a dielectric liner to form a deep capacitor trench isolation structure. Contact via structures are formed through the buried insulator layer and a top semiconductor layer and onto the portion of the buried conductive layer, which constitutes a buried conductive conduit. The deep capacitor trench isolation structure may be formed concurrently with at least one deep trench capacitor. A patterned portion of the top semiconductor layer may be employed as an additional conductive conduit for signal transmission. Further, the deep capacitor trench isolation structure may include a conductive portion, which can be electrically biased to control the impedance of the signal path including the buried conductive conduit.

Abstract translation: 在绝缘体上半导体（SOI）衬底的掩埋绝缘体层下方形成掩埋导电层。 形成横向围绕埋入导电层的一部分的深隔离沟槽，并且至少填充有介电衬垫以形成深电容器沟槽隔离结构。 通过结构的接触通过掩埋绝缘体层和顶部半导体层形成，并且形成在掩埋导电层的构成掩埋导电导管的部分上。 深电容器沟槽隔离结构可以与至少一个深沟槽电容器同时形成。 可以使用顶部半导体层的图案化部分作为用于信号传输的附加导电管道。 此外，深电容器沟槽隔离结构可以包括导电部分，导电部分可被电偏置以控制包括埋入导电导管的信号路径的阻抗。

公开(公告)号：US20160172378A1

公开(公告)日：2016-06-16

申请号：US14566779

申请日：2014-12-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anthony I. Chou ,  Arvind Kumar ,  Sungjae Lee

IPC: H01L27/12 ,  H01L29/423 ,  H01L21/28 ,  H01L21/311 ,  H01L21/84 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L27/1211 ,  H01L21/28017 ,  H01L21/845 ,  H01L29/0649 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/6653

Abstract: A gate contact with reduced contact resistance is provided by increasing contact area between the gate contact and a gate conductive portion of a gate structure. The gate contact forms a direct contact with a topmost surface and at least portions of outermost sidewalls of a portion of the gate conductive portion, thus increasing the contact area between the gate contact and the gate structure. The gate contact area of the present application can be further increased by completely surrounding a portion of the gate conductive portion of the gate structure with the gate contact.

Abstract translation: 通过增加栅极接触和栅极结构的栅极导电部分之间的接触面积来提供具有降低的接触电阻的栅极接触。 栅极接触形成与栅极导电部分的一部分的最顶表面和最外侧壁的至少部分的直接接触，从而增加了栅极接触和栅极结构之间的接触面积。 通过用栅极接触完全围绕栅极结构的栅极导电部分的一部分，可以进一步提高本申请的栅极接触面积。

公开(公告)号：US09923082B2

公开(公告)日：2018-03-20

申请号：US15453939

申请日：2017-03-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Anthony I. Chou ,  Judson R. Holt ,  Arvind Kumar ,  Henry K. Utomo

IPC: H01L29/66 ,  H01L21/84 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L21/306 ,  H01L29/165 ,  H01L29/78

CPC classification number: H01L29/66636 ,  H01L21/30604 ,  H01L21/84 ,  H01L29/0649 ,  H01L29/0688 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66742 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/786

Abstract: The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a partially depleted semiconductor-on-insulator (SOI) junction isolation structure using a nonuniform trench shape formed by reactive ion etching (RIE) and crystallographic wet etching. The nonuniform trench shape may reduce back channel leakage by providing an effective channel directly below a gate stack having a width that is less than a width of an effective back channel directly above the isolation layer.

公开(公告)号：US09508826B2

公开(公告)日：2016-11-29

申请号：US14307575

申请日：2014-06-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anthony I. Chou ,  Arvind Kumar ,  Sungjae Lee

IPC: H01L29/66 ,  H01L29/40 ,  H01L29/423 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/49 ,  H01L21/28 ,  H01L21/02 ,  H01L21/283 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/3213 ,  H01L29/51 ,  H01L21/84 ,  H01L27/088 ,  H01L21/8238 ,  H01L27/12

CPC classification number: H01L29/66545 ,  H01L21/02107 ,  H01L21/28132 ,  H01L21/28158 ,  H01L21/283 ,  H01L21/31111 ,  H01L21/3205 ,  H01L21/32133 ,  H01L21/32139 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/401 ,  H01L29/4232 ,  H01L29/42356 ,  H01L29/4238 ,  H01L29/4958 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/785

Abstract: After formation of a gate cavity straddling at least one semiconductor material portion, a gate dielectric layer and at least one work function material layer is formed over the gate dielectric layer. The at least one work function material layer and the gate dielectric layer are patterned such that remaining portions of the at least one work function material layer are present only in proximity to the at least one semiconductor material portion. A conductive material having a greater conductivity than the at least one work function material layer is deposited in remaining portions of the gate cavity. The conductive material portion within a replacement gate structure has the full width of the replacement gate structure in regions from which the at least one work function material layer and the gate dielectric layer are removed.

公开(公告)号：US09412759B2

公开(公告)日：2016-08-09

申请号：US14566779

申请日：2014-12-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anthony I. Chou ,  Arvind Kumar ,  Sungjae Lee

IPC: H01L27/12 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L21/311 ,  H01L21/84 ,  H01L21/28

CPC classification number: H01L27/1211 ,  H01L21/28017 ,  H01L21/845 ,  H01L29/0649 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/6653

Abstract: A gate contact with reduced contact resistance is provided by increasing contact area between the gate contact and a gate conductive portion of a gate structure. The gate contact forms a direct contact with a topmost surface and at least portions of outermost sidewalls of a portion of the gate conductive portion, thus increasing the contact area between the gate contact and the gate structure. The gate contact area of the present application can be further increased by completely surrounding a portion of the gate conductive portion of the gate structure with the gate contact.

Abstract translation: 通过增加栅极接触和栅极结构的栅极导电部分之间的接触面积来提供具有降低的接触电阻的栅极接触。 栅极接触形成与栅极导电部分的一部分的最顶表面和最外侧壁的至少部分的直接接触，从而增加了栅极接触和栅极结构之间的接触面积。 通过用栅极接触完全围绕栅极结构的栅极导电部分的一部分，可以进一步提高本申请的栅极接触面积。

公开(公告)号：US09450072B2

公开(公告)日：2016-09-20

申请号：US14519615

申请日：2014-10-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anthony I. Chou ,  Arvind Kumar ,  Sungjae Lee

IPC: H01L21/027 ,  H01L29/66 ,  H01L29/40 ,  H01L29/423 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/49 ,  H01L21/28 ,  H01L21/02 ,  H01L21/283 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/3213 ,  H01L29/51 ,  H01L21/84 ,  H01L27/088 ,  H01L21/8238 ,  H01L27/12

CPC classification number: H01L29/66545 ,  H01L21/02107 ,  H01L21/28132 ,  H01L21/28158 ,  H01L21/283 ,  H01L21/31111 ,  H01L21/3205 ,  H01L21/32133 ,  H01L21/32139 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/401 ,  H01L29/4232 ,  H01L29/42356 ,  H01L29/4238 ,  H01L29/4958 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/785

Abstract: After formation of a gate cavity straddling at least one semiconductor material portion, a gate dielectric layer and at least one work function material layer is formed over the gate dielectric layer. The at least one work function material layer and the gate dielectric layer are patterned such that remaining portions of the at least one work function material layer are present only in proximity to the at least one semiconductor material portion. A conductive material having a greater conductivity than the at least one work function material layer is deposited in remaining portions of the gate cavity. The conductive material portion within a replacement gate structure has the full width of the replacement gate structure in regions from which the at least one work function material layer and the gate dielectric layer are removed.

Abstract translation: 在形成跨越至少一个半导体材料部分的栅极腔形成之后，在栅极介电层上形成栅极电介质层和至少一个功函数材料层。 图案化至少一个功函数材料层和栅介电层，使得至少一个功函数材料层的剩余部分仅存在于至少一个半导体材料部分附近。 具有比至少一个功函数材料层更大的导电性的导电材料沉积在栅极腔的剩余部分中。 替代栅极结构中的导电材料部分在去除了至少一个功函数材料层和栅极电介质层的区域中具有替换栅极结构的全宽。

公开(公告)号：US09627480B2

公开(公告)日：2017-04-18

申请号：US14315385

申请日：2014-06-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anthony I. Chou ,  Judson R. Holt ,  Arvind Kumar ,  Henry K. Utomo

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/786 ,  H01L29/78 ,  H01L29/165

CPC classification number: H01L29/66636 ,  H01L21/30604 ,  H01L21/84 ,  H01L29/0649 ,  H01L29/0688 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66742 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/786

Abstract: The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a partially depleted semiconductor-on-insulator (SOI) junction isolation structure using a nonuniform trench shape formed by reactive ion etching (RIE) and crystallographic wet etching. The nonuniform trench shape may reduce back channel leakage by providing an effective channel directly below a gate stack having a width that is less than a width of an effective back channel directly above the isolation layer.

公开(公告)号：US20170076991A1

公开(公告)日：2017-03-16

申请号：US14853373

申请日：2015-09-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Anthony I. Chou ,  Judson R. Holt ,  Arvind Kumar ,  Henry K. Utomo

IPC: H01L21/8238 ,  H01L21/266 ,  H01L27/092 ,  H01L29/78 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L21/265 ,  H01L29/08

CPC classification number: H01L21/823814 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/7848

Abstract: An aspect of the disclosure provides for an asymmetric semiconductor device. The asymmetric semiconductor device may comprise: a substrate; and a fin-shaped field effect transistor (FINFET) disposed on the substrate, the FINFET including: a set of fins disposed proximate a gate; a first epitaxial region disposed on a source region on the set of fins, the first epitaxial region having a first height; and a second epitaxial region disposed on a drain region on the set of fins, the second epitaxial region having a second height, wherein the first height is distinct from the second height.

Abstract translation: 本公开的一个方面提供了一种不对称半导体器件。 不对称半导体器件可以包括：衬底; 以及设置在所述衬底上的鳍状场效应晶体管（FINFET），所述FINFET包括：设置在栅极附近的一组翅片; 第一外延区域，设置在所述一组鳍片上的源极区域上，所述第一外延区域具有第一高度; 以及设置在所述散热片组上的漏极区域上的第二外延区域，所述第二外延区域具有第二高度，其中所述第一高度与所述第二高度不同。