公开(公告)号：US10580857B2

公开(公告)日：2020-03-03

申请号：US16010694

申请日：2018-06-18

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Yanzhen Wang ,  Xinyuan Dou ,  Hongliang Shen ,  Sipeng Gu

IPC: H01L29/06 ,  H01L21/02 ,  H01L29/78 ,  H01L29/66 ,  H01L21/762

Abstract: A shallow trench isolation (STI) structure is formed from a conventional STI trench structure of a first dielectric material extending into the substrate. The conventional STI structure undergoes further processing: removing a first portion of the dielectric material and adjacent portions of the semiconductor substrate to create a first recess, and then removing another portion of the dielectric material to create a second recess in just the dielectric material. A nitride spacer layer is formed above the remaining dielectric material and on the sidewalls of the substrate. A second dielectric material is formed on the spacer layer and fills the remainder of first and second recesses to a lever above the substrate. A nitride capping layer and another dielectric layer are disposed above the second material, thereby substantially encasing the STI structure in nitride. This provides a taller STI structure that results in a better fin profile during a subsequent fin reveal process.

公开(公告)号：US10522679B2

公开(公告)日：2019-12-31

申请号：US15797380

申请日：2017-10-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ashish Kumar Jha ,  Hong Yu ,  Xinyuan Dou ,  Xusheng Wu ,  Dongil Choi ,  Edmund K. Banghart ,  Md Khaled Hassan

IPC: H01L29/78 ,  H01L29/06 ,  H01L27/092 ,  H01L21/762 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/308 ,  H01L21/3065 ,  H01L21/311

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to selective shallow trench isolation (STI) fill material for stress engineering in semiconductor structures and methods of manufacture. The structure includes a single diffusion break (SDB) region having at least one shallow trench isolation (STI) region with a stress fill material within a recess of the at least one STI region. The stress fill material imparts a stress on a gate structure adjacent to the at least one STI region.

公开(公告)号：US20190386100A1

公开(公告)日：2019-12-19

申请号：US16010694

申请日：2018-06-18

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Yanzhen Wang ,  Xinyuan Dou ,  Hongliang Shen ,  Sipeng Gu

IPC: H01L29/06 ,  H01L29/78 ,  H01L21/762 ,  H01L21/02 ,  H01L29/66

Abstract: A shallow trench isolation (STI) structure is formed from a conventional STI trench structure of a first dielectric material extending into the substrate. The conventional STI structure undergoes further processing: removing a first portion of the dielectric material and adjacent portions of the semiconductor substrate to create a first recess, and then removing another portion of the dielectric material to create a second recess in just the dielectric material. A nitride spacer layer is formed above the remaining dielectric material and on the sidewalls of the substrate. A second dielectric material is formed on the spacer layer and fills the remainder of first and second recesses to a lever above the substrate. A nitride capping layer and another dielectric layer are disposed above the second material, thereby substantially encasing the STI structure in nitride. This provides a taller STI structure that results in a better fin profile during a subsequent fin reveal process.

公开(公告)号：US10347531B2

公开(公告)日：2019-07-09

申请号：US15438828

申请日：2017-02-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Sipeng Gu ,  Xusheng Wu ,  Xinyuan Dou ,  Xiaobo Chen ,  Guoliang Zhu ,  Wenhe Lin ,  Jeffrey Chee

IPC: H01L21/768 ,  H01L23/535 ,  H01L23/532

Abstract: Disclosed are a method of forming an integrated circuit (IC) structure with robust metal plugs and the resulting IC structure. In the method, openings are formed in an interlayer dielectric layer to expose semiconductor device surfaces. The openings are lined with a two-layer liner, which includes conformal metal and barrier layers, and subsequently filled with a metal layer. However, instead of waiting until after the liner is formed to perform a silicidation anneal, as is conventionally done, the silicidation anneal is performed between deposition of the two liner layers. This is particularly useful because, as determined by the inventors, performing the silicidation anneal prior to depositing the conformal barrier layer prevents the formation of microcracks in the conformal barrier layer. Prevention of such microcracks, in turn, prevents any metal from the metal layer from protruding into the area between the two liner layers and/or completely through the liner.

公开(公告)号：US10090382B1

公开(公告)日：2018-10-02

申请号：US15811957

申请日：2017-11-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hong Yu ,  Xinyuan Dou ,  Hui Zhan ,  Zhenyu Hu

IPC: H01L29/06 ,  H01L21/8234 ,  H01L21/3213 ,  H01L27/088 ,  H01L27/02 ,  H01L21/308 ,  H01L21/762 ,  H01L21/027

Abstract: The disclosure relates to forming single diffusion break (SDB) and end isolation regions in an integrated circuit (IC) structure, and resulting structures. An IC structure according to the disclosure includes: a plurality of fins positioned on a substrate; a plurality of gate structures each positioned on the plurality of fins and extending transversely across the plurality of fins; an insulator region positioned on and extending transversely across the plurality of fins between a pair of the plurality of gate structures; at least one single diffusion break (SDB) region positioned within the insulator region and one of the plurality of fins, the at least one SDB extending from an upper surface of the substrate to an upper surface of the insulator region; and an end isolation region positioned laterally adjacent to a lateral end of one of the plurality of gate structures.

公开(公告)号：US10043713B1

公开(公告)日：2018-08-07

申请号：US15591814

申请日：2017-05-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xinyuan Dou ,  Hong Yu ,  Zhenyu Hu ,  Xing Zhang

IPC: H01L21/84 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/10 ,  H01L29/423

Abstract: Methods of reducing the SC GH on a FinFET device while protecting the LC devices and the resulting devices are provided. Embodiments include forming an ILD over a substrate of a FinFET device, the ILD having a SC region and a LC region; forming a SC gate and a LC gate within the SC and LC regions, respectively, an upper surface of the SC and LC gates being substantially coplanar with an upper surface of the ILD; forming a lithography stack over the LC region; recessing the SC gate; stripping the lithography stack; forming a SiN cap layer over the SC and LC regions; forming a TEOS layer over the SiN cap layer; and planarizing the TEOS layer.

公开(公告)号：US10014296B1

公开(公告)日：2018-07-03

申请号：US15487636

申请日：2017-04-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xinyuan Dou ,  Hong Yu ,  Sipeng Gu ,  Yanzhen Wang

IPC: H01L21/761 ,  H01L29/165 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/02 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L21/762

CPC classification number: H01L27/0886 ,  H01L21/02532 ,  H01L21/761 ,  H01L21/76224 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823475 ,  H01L21/823481 ,  H01L29/0646 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

Abstract: Disclosed is a method of forming a semiconductor structure that includes one or more fin-type field effect transistors (FINFETs) and single-diffusion break (SDB) type isolation regions that are within a semiconductor fin and that define the active device region(s) for the FINFET(s). The isolation regions are formed so that they include a semiconductor liner. The semiconductor liner ensures that, when a source/drain recess is formed immediately adjacent to the isolation region, the bottom and opposing sides of the source/drain recess will have semiconductor surfaces onto which epitaxial semiconductor material for a source/drain region is grown. As a result, the angle of the top surface of the source/drain region relative to the top surface of the semiconductor fin is minimized. Thus, the risk that a subsequently formed source/drain contact will not reach the source/drain region is also minimized. Also disclosed is a semiconductor structure formed according to the method.