公开(公告)号：US10741685B2

公开(公告)日：2020-08-11

申请号：US16137739

申请日：2018-09-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Robert Gauthier, Jr. ,  Souvick Mitra ,  Alain Loiseau ,  Tsai Tsung-Che ,  Mickey Yu ,  You Li

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/06 ,  H01L21/8234 ,  H01L27/24

Abstract: Structures for laterally-diffused metal-oxide-semiconductor devices and drain-extended metal-oxide-semiconductor devices, as well as methods of forming laterally-diffused metal-oxide-semiconductor devices and drain-extended metal-oxide-semiconductor devices. A gate electrode is arranged to extend about a semiconductor fin projecting from a substrate. A drain region is arranged in the substrate, and a source region is coupled with the semiconductor fin. The source region is arranged over the semiconductor fin. A drift region is arranged in the substrate between the drain region and the semiconductor fin. The drain region, source region, and drift region have a given conductivity type. The drift region has a lower electrical conductivity than the drain region.

公开(公告)号：US10692852B2

公开(公告)日：2020-06-23

申请号：US16171760

申请日：2018-10-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Alain Loiseau ,  You Li ,  Mickey Yu ,  Tsung-Che Tsai ,  Souvick Mitra ,  Robert J. Gauthier, Jr.

IPC: H01L29/74 ,  H01L27/02 ,  H01L21/762 ,  H01L29/06 ,  H01L29/66

Abstract: Silicon-controlled rectifiers and methods for forming a silicon-controlled rectifier. A first well of a first conductivity type is arranged in a substrate, and second and third wells of a second conductivity type are arranged in the substrate between the first well and the top surface of the substrate. A deep trench isolation region is laterally arranged between the first well of the second conductivity type and the second well of the second conductivity type. The second well is adjoined with the first well along a first interface, the third well is adjoined with the first well along a second interface, and the deep trench isolation region extends the top surface of the substrate past the first interface and the second interface and into the first well. A doped region of the first conductivity type is arranged in the substrate between the second well and the top surface of the substrate.

公开(公告)号：US20200135715A1

公开(公告)日：2020-04-30

申请号：US16171760

申请日：2018-10-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Alain Loiseau ,  You Li ,  Mickey Yu ,  Tsung-Che Tsai ,  Souvick Mitra ,  Robert J. Gauthier, JR.

IPC: H01L27/02 ,  H01L29/74 ,  H01L29/66 ,  H01L29/06 ,  H01L21/762

Abstract: Silicon-controlled rectifiers and methods for forming a silicon-controlled rectifier. A first well of a first conductivity type is arranged in a substrate, and second and third wells of a second conductivity type are arranged in the substrate between the first well and the top surface of the substrate. A deep trench isolation region is laterally arranged between the first well of the second conductivity type and the second well of the second conductivity type. The second well is adjoined with the first well along a first interface, the third well is adjoined with the first well along a second interface, and the deep trench isolation region extends the top surface of the substrate past the first interface and the second interface and into the first well. A doped region of the first conductivity type is arranged in the substrate between the second well and the top surface of the substrate.

公开(公告)号：US10541236B2

公开(公告)日：2020-01-21

申请号：US16018549

申请日：2018-06-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Souvick Mitra ,  Mickey Yu ,  Alain F. Loiseau ,  You Li ,  Robert J. Gauthier, Jr. ,  Tsung-Che Tsai

IPC: H01L27/02 ,  H01L23/60 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L29/66

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to electrostatic discharge structures with reduced capacitance and methods of manufacture. The structure includes: a plurality of fin structures provided in at least one N+ type region and at least one P+ region; and a plurality of gate structures disposed over the plurality of fin structures and within the at least one N+ type region and one P+ region, the plurality of gate structures being separated in a lengthwise direction between the at least one N+ type region and the least one P+ region.

公开(公告)号：US10290626B1

公开(公告)日：2019-05-14

申请号：US15870238

申请日：2018-01-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： You Li ,  Alain Loiseau ,  Tsung-Che Tsai ,  Mickey Yu ,  Souvick Mitra ,  Robert Gauthier, Jr.

IPC: H01L27/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/285 ,  H01L29/78 ,  H01L29/10 ,  H01L29/08 ,  H01L23/535

Abstract: Methods of integrating a HV ESD PNP bipolar transistor in a VFET process and the resulting devices are provided. Embodiments include forming a DNW region in a portion of a p-sub; forming a HVPDDD region in a portion of the DNW region; forming a first and a second NW in a portion of the DNW region, the second NW between the first NW and the HVPDDD region and laterally separated from the HVPDDD region; forming a PW in a portion of the HVPDDD region; forming an N+ implant in a portion of the first NW and a P+ implant in a portion of the PW; forming a first, a second and a third fin structures over the first and the second NW and the PW, respectively; and forming a N+ S/D, a P+ S/D and a P+ S/D over the first, the second and the third fin structures, respectively.

公开(公告)号：US10008491B1

公开(公告)日：2018-06-26

申请号：US15655274

申请日：2017-07-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： You Li ,  Robert J. Gauthier, Jr. ,  Souvick Mitra ,  Mickey Yu

IPC: H01L27/02 ,  H01L29/861 ,  H01L23/66

CPC classification number: H01L27/0262 ,  H01L23/66 ,  H01L27/0255 ,  H01L29/861

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to low capacitance electrostatic discharge (ESD) devices and methods of manufacture. The structure includes: a first structure comprising a pattern of a first diffusion region, a second diffusion region and a third diffusion region partly extending over a first well; and a second structure comprising a fourth diffusion region in a second well electrically connecting to the first structure to form a silicon controlled rectifier (SCR) on a bulk region of a substrate.

公开(公告)号：US09704852B2

公开(公告)日：2017-07-11

申请号：US15140516

申请日：2016-04-28

Applicant: GLOBALFOUNDRIES INC.

Inventor： Robert J. Gauthier, Jr. ,  Tom C. Lee ,  You Li ,  Rahul Mishra ,  Souvick Mitra ,  Andreas Scholze

IPC: H01L29/66 ,  H01L29/15 ,  H01L27/088 ,  H01L27/02 ,  H01L27/06 ,  H01L29/78 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L27/0255 ,  H01L27/0266 ,  H01L27/027 ,  H01L27/0288 ,  H01L27/0629 ,  H01L29/0649 ,  H01L29/0684 ,  H01L29/42372 ,  H01L29/7827 ,  H01L29/785 ,  H01L29/7855 ,  H01L2029/7858

Abstract: Field effect diode structures utilize a junction structure that has an L-shape in cross-section (a fin extending from a planar portion). An anode is positioned at the top surface of the fin, and a cathode is positioned at the end surface of the planar portion. The perpendicularity of the fin and the planar portion cause the anode and cathode to be perpendicular to one another. A first gate insulator contacts the fin between the top surface and the planar portion. A first gate conductor contacts the first gate insulator, and the first gate insulator is between the first gate conductor and the surface of the fin. Additionally, a second gate insulator contacts the planar portion between the end surface and the fin. A second gate conductor contacts the second gate insulator, and the second gate insulator is between the second gate conductor and the surface of the planar portion.