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    COMPACT MEMORY-IN-PIXEL DISPLAY STRUCTURE
    11.
    发明申请
    COMPACT MEMORY-IN-PIXEL DISPLAY STRUCTURE 有权

    公开(公告)号：US20250118245A1

    公开(公告)日：2025-04-10

    申请号：US18482114

    申请日：2023-10-06

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Juhan Kim ,  Sanjay Raj Parihar ,  Mahbub Rashed ,  Zahir Yilmaz Alpaslan

    IPC: G09G3/32 ,  G11C11/419 ,  H10B10/00

    Abstract: Disclosed are a pixel and a compact memory-in-pixel display (e.g., implemented in a fully-depleted semiconductor-on-insulator processing technology platform). A block of electronic components for a pixel includes a memory cell array, a driving circuit for an LED, and a logic circuit connected between the memory cell array and driving circuit. The memory cell array is above a Pwell, the driving circuit is above an adjacent Nwell, and the logic circuit includes P-type transistors on the Nwell and N-type transistors on the Pwell. A pixel array is above alternating P and N wells with a single buried Nwell below. Specifically, each column of pixels is above adjacent elongated P and N wells and, within each column, adjacent pixels have mirrored layouts. Furthermore, adjacent columns of pixels are above two elongated wells of one type and a shared elongated well of the opposite type therebetween and the adjacent columns have mirrored layouts.

    System and method employing power-optimized timing closure
    12.
    发明授权
    System and method employing power-optimized timing closure 有权

    公开(公告)号：US12260163B2

    公开(公告)日：2025-03-25

    申请号：US17679178

    申请日：2022-02-24

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Navneet Jain ,  Mahbub Rashed

    IPC: G06F30/39 ,  G06F30/392 ,  G06F30/398 ,  G06F111/04 ,  G06F111/20

    Abstract: Disclosed are embodiments of a computer-aided design system and corresponding method for power-optimized timing closure of an integrated circuit (IC) design. In the embodiments, a cell library includes sets of cells, where each cell in the same set has the same internal structure but different combinations of cell boundary isolation structures associated with different passive delay values. Timing closure includes replacement of a cell in a previously generated layout with another cell from the same set in order to adjust delay (e.g., increase delay) of a data signal or clock signal and, thereby facilitate fixing of a previously identified violation of a timing constraint. By eliminating or at least minimizing the need to insert buffer and/or inverter cells into a layout to add delay to a data signal and/or a clock signal during timing closure, the embodiments avoid or at least limit concurrent increases in power consumption and area consumption.

    POST-MANUFACTURE LATCH TIMING CONTROL BLOCKS IN PIPELINED PROCESSORS
    13.
    发明公开
    POST-MANUFACTURE LATCH TIMING CONTROL BLOCKS IN PIPELINED PROCESSORS 审中-公开

    公开(公告)号：US20230341888A1

    公开(公告)日：2023-10-26

    申请号：US17726171

    申请日：2022-04-21

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Vivek Raj ,  Sunil Kumar ,  Shivraj G. Dharne ,  Mahbub Rashed

    IPC: G06F1/10 ,  G06F15/78

    CPC classification number: G06F1/10 ,  G06F15/7839

    Abstract: An apparatus includes a series of pipeline stages that have logic components connected to supply output data to latch components, timing correction blocks connected to the latch components, and a memory component connected to supply a correction pattern to the timing correction blocks. The timing correction blocks have a buffer connected to a multiplexor. The correction pattern controls whether the multiplexor receives an adjusted clock signal through the buffer to control whether the timing correction blocks supply an unadjusted clock signal or the adjusted clock signal to the latch components.

    SYSTEM AND METHOD EMPLOYING POWER-OPTIMIZED TIMING CLOSURE
    14.
    发明公开
    SYSTEM AND METHOD EMPLOYING POWER-OPTIMIZED TIMING CLOSURE 审中-公开

    公开(公告)号：US20230267259A1

    公开(公告)日：2023-08-24

    申请号：US17679178

    申请日：2022-02-24

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Navneet Jain ,  Mahbub Rashed

    IPC: G06F30/392 ,  G06F30/398

    CPC classification number: G06F30/392 ,  G06F30/398 ,  G06F2111/20

    Abstract: Disclosed are embodiments of a computer-aided design system and corresponding method for power-optimized timing closure of an integrated circuit (IC) design. In the embodiments, a cell library includes sets of cells, where each cell in the same set has the same internal structure but different combinations of cell boundary isolation structures associated with different passive delay values. Timing closure includes replacement of a cell in a previously generated layout with another cell from the same set in order to adjust delay (e.g., increase delay) of a data signal or clock signal and, thereby facilitate fixing of a previously identified violation of a timing constraint. By eliminating or at least minimizing the need to insert buffer and/or inverter cells into a layout to add delay to a data signal and/or a clock signal during timing closure, the embodiments avoid or at least limit concurrent increases in power consumption and area consumption.

    SEMICONDUCTOR STRUCTURE INCLUDING SECTIONED WELL REGION
    15.
    发明公开
    SEMICONDUCTOR STRUCTURE INCLUDING SECTIONED WELL REGION 审中-公开

    公开(公告)号：US20230163134A1

    公开(公告)日：2023-05-25

    申请号：US17533402

    申请日：2021-11-23

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Navneet Jain ,  Nigel Chan ,  Mahbub Rashed

    IPC: H01L27/12

    CPC classification number: H01L27/1207

    Abstract: Disclosed is a semiconductor structure including a substrate with a first type conductivity (e.g., a P− silicon substrate); a deep well region within the substrate and having a second type conductivity (e.g., a deep Nwell); alternating stripes of first and second well regions (e.g., of Pwells and Nwells with each Pwell positioned laterally between and abutting two Nwells) within the substrate above and traversing the deep well region; and an isolation region (e.g., an Nwell-type isolation region) dividing a first well region (e.g., a Pwell) into sections. Since the sectioned first well region has the first type conductivity and since the isolation region, the deep well region below, and the adjacent well regions on either side have the second type conductivity, the different sections of the sectioned well region are electrically isolated and devices formed on an insulator layer above the different sections can be subjected to different back-biasing conditions.

    LOW-LEAKAGE SENSE CIRCUIT, MEMORY CIRCUIT INCORPORATING THE LOW-LEAKAGE SENSE CIRCUIT, AND METHOD
    17.
    发明申请
    LOW-LEAKAGE SENSE CIRCUIT, MEMORY CIRCUIT INCORPORATING THE LOW-LEAKAGE SENSE CIRCUIT, AND METHOD 有权

    公开(公告)号：US20220215872A1

    公开(公告)日：2022-07-07

    申请号：US17143193

    申请日：2021-01-07

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Vivek Raj ,  Shivraj G. Dharne ,  Uttam K. Saha ,  Mahbub Rashed

    IPC: G11C11/419 ,  G11C11/412 ,  H01L27/11

    Abstract: A disclosed sense circuit for a memory circuit includes sense amplifiers that detect differences in voltage levels on complementary bitlines during read operations. Instead of the sense amplifiers having built-in footer devices that lead to significant leakage, the sense circuit incorporates a common footer device for all sense amplifiers. To ensure that this footer device has sufficient drive strength to enable voltage differential detection by each sense amplifier, the sense circuit also includes a sense signal generation and boost circuit (SSG&B circuit) that generates a sense mode control signal (SEN) to control the on/off states of the footer device and that further boosts SEN, at the appropriate time, to increase the drive current. By using the common footer device and the SSG&B circuit, leakage from the sense circuit is reduced during a pre-charge operation mode without sacrificing performance during a read operation mode. Also disclosed are associated method embodiments.

    AREA-EFFICIENT FULLY DEPLETED SEMICONDUCTOR-ON-INSULATOR STRUCTURE WITH MIXED THRESHOLD VOLTAGE TRANSISTORS
    18.
    发明申请
    AREA-EFFICIENT FULLY DEPLETED SEMICONDUCTOR-ON-INSULATOR STRUCTURE WITH MIXED THRESHOLD VOLTAGE TRANSISTORS 有权

    公开(公告)号：US20250120175A1

    公开(公告)日：2025-04-10

    申请号：US18482107

    申请日：2023-10-06

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Navneet K. Jain ,  Juhan Kim ,  Mahbub Rashed

    IPC: H01L27/118 ,  H03K19/20

    Abstract: Disclosed is a fully depleted semiconductor-on-insulator structure including a buried Nwell in a substrate below P-type and N-type well regions, an insulator layer on the substrate, and mixed threshold voltage transistors on the insulator layer above at least one of the well regions. An Nwell can be connected to receive a positive bias voltage with any NFET and any PFET above being a FBB LVT/SLVT NFET and a RBB RVT/HVT PFET, respectively. A Pwell can be connected to receive another positive bias voltage less than the positive bias voltage on the Nwell with any NFET and any PFET above being a FBB RVT/HVT NFET and a RBB LVT/SLVT PFET, respectively. Additionally, or alternatively, a Pwell can be connected to receive a negative bias voltage with any NFET and any PFET above being a RBB RVT/HVT NFET and a FBB LVT/SLVT PFET, respectively.

    Compact memory-in-pixel display structure
    19.
    发明授权
    Compact memory-in-pixel display structure 有权

    公开(公告)号：US12272299B1

    公开(公告)日：2025-04-08

    申请号：US18482114

    申请日：2023-10-06

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Juhan Kim ,  Sanjay Raj Parihar ,  Mahbub Rashed ,  Zahir Yilmaz Alpaslan

    IPC: G09G3/32 ,  G11C11/419 ,  H10B10/00

    Abstract: Disclosed are a pixel and a compact memory-in-pixel display (e.g., implemented in a fully-depleted semiconductor-on-insulator processing technology platform). A block of electronic components for a pixel includes a memory cell array, a driving circuit for an LED, and a logic circuit connected between the memory cell array and driving circuit. The memory cell array is above a Pwell, the driving circuit is above an adjacent Nwell, and the logic circuit includes P-type transistors on the Nwell and N-type transistors on the Pwell. A pixel array is above alternating P and N wells with a single buried Nwell below. Specifically, each column of pixels is above adjacent elongated P and N wells and, within each column, adjacent pixels have mirrored layouts. Furthermore, adjacent columns of pixels are above two elongated wells of one type and a shared elongated well of the opposite type therebetween and the adjacent columns have mirrored layouts.

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