公开(公告)号：US11784224B2

公开(公告)日：2023-10-10

申请号：US17455290

申请日：2021-11-17

Applicant: GlobalFoundries U.S. Inc.

Inventor： Hong Yu ,  Jagar Singh ,  Zhenyu Hu ,  John J. Pekarik

IPC: H01L29/10 ,  H01L29/417 ,  H01L29/423 ,  H01L29/40 ,  H01L29/737 ,  H01L29/66 ,  H01L29/735 ,  H01L29/08

CPC classification number: H01L29/1008 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/401 ,  H01L29/41708 ,  H01L29/42304 ,  H01L29/6625 ,  H01L29/66242 ,  H01L29/735 ,  H01L29/737

Abstract: The disclosure provides a lateral bipolar transistor structure with a base layer over a semiconductor buffer, and related methods. A lateral bipolar transistor structure may include an emitter/collector (E/C) layer over an insulator. The E/C layer has a first doping type. A semiconductor buffer is adjacent the insulator. A base layer is on the semiconductor buffer and adjacent the E/C layer, the base layer including a lower surface below the E/C layer and an upper surface above the E/C layer. The base layer has a second doping type opposite the first doping type.

公开(公告)号：US11469178B2

公开(公告)日：2022-10-11

申请号：US17126921

申请日：2020-12-18

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Anthony K. Stamper ,  John J. Ellis-Monaghan ,  Steven M. Shank ,  John J. Pekarik ,  Vibhor Jain

IPC: H01L23/525 ,  H01L27/12 ,  H01L23/532

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a metal-free fuse structure and methods of manufacture. The structure includes: a first metal-free fuse structure comprising a top semiconductor material of semiconductor-on-insulator (SOI) technologies, the top semiconductor material including end portions with a first electrical resistance and a fuse portion of a second, higher electrical resistance electrically connected to the end portions; and a second metal-free fuse structure comprising the top semiconductor material of semiconductor-on-insulator (SOI) technologies, the top semiconductor material of the second metal-free fuse structure including at least a fuse portion of a lower electrical resistance than the second, higher electrical resistance.

公开(公告)号：US11217685B2

公开(公告)日：2022-01-04

申请号：US16909376

申请日：2020-06-23

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Herbert Ho ,  Vibhor Jain ,  John J. Pekarik ,  Claude Ortolland ,  Judson R. Holt ,  Qizhi Liu ,  Viorel Ontalus

IPC: H01L29/737 ,  H01L29/66 ,  H01L29/08

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a device with a marker layer and methods of manufacture. The device includes: a collector region; an intrinsic base region above the collector region; an emitter region comprising emitter material and a marker layer vertically between the intrinsic base region and the emitter material; and an extrinsic base region in electrical contact with the intrinsic base region.

公开(公告)号：US11145725B2

公开(公告)日：2021-10-12

申请号：US16823005

申请日：2020-03-18

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Qizhi Liu ,  Vibhor Jain ,  Judson R. Holt ,  Herbert Ho ,  Claude Ortolland ,  John J. Pekarik

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/737 ,  H01L29/08

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a heterojunction bipolar transistor and methods of manufacture. The structure includes: a sub-collector region; a collector region in electrical connection to the sub-collector region; an emitter located adjacent to the collector region and comprising emitter material, recessed sidewalls on the emitter material and an extension region extending at an upper portion of the emitter material above the recessed sidewalls; and an extrinsic base separated from the emitter by the recessed sidewalls.

公开(公告)号：US11848192B2

公开(公告)日：2023-12-19

申请号：US17124012

申请日：2020-12-16

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Vibhor Jain ,  Anthony K. Stamper ,  Steven M. Shank ,  John J. Pekarik

IPC: H01L29/737 ,  H01L29/06

CPC classification number: H01L29/7373 ,  H01L29/0649 ,  H01L29/7371

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a heterojunction bipolar transistor having an emitter base junction with a silicon-oxygen lattice interface and methods of manufacture. The device includes: a collector region buried in a substrate; shallow trench isolation regions, which isolate the collector region buried in the substrate; a base region on the substrate and over the collector region; an emitter region composed of a single crystalline of semiconductor material and located over with the base region; and an oxide interface at a junction of the emitter region and the base region.

公开(公告)号：US11791334B2

公开(公告)日：2023-10-17

申请号：US17075056

申请日：2020-10-20

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Vibhor Jain ,  John J. Ellis-Monaghan ,  Anthony K. Stamper ,  Steven M. Shank ,  John J. Pekarik

IPC: H01L27/08 ,  H01L27/082 ,  H01L27/06 ,  H01L29/737 ,  H01L29/06

CPC classification number: H01L27/082 ,  H01L27/0647 ,  H01L29/0646 ,  H01L29/737

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors (HBTs) with a buried trap rich isolation region and methods of manufacture. The structure includes: a first heterojunction bipolar transistor; a second heterojunction bipolar transistor; and a trap rich isolation region embedded within a substrate underneath both the first heterojunction bipolar transistor and the second heterojunction bipolar transistor.

公开(公告)号：US11646348B2

公开(公告)日：2023-05-09

申请号：US17473164

申请日：2021-09-13

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： John J. Pekarik ,  Vibhor Jain

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/08 ,  H01L29/737

CPC classification number: H01L29/1004 ,  H01L29/0817 ,  H01L29/66242 ,  H01L29/7371

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a heterojunction bipolar transistor and methods of manufacture. The structure includes: a sub-collector region; a collector region above the sub-collector region; an intrinsic base region composed of intrinsic base material located above the collector region; an emitter located above and separated from the intrinsic base material; and a raised extrinsic base having a stepped configuration and separated from and self-aligned to the emitter.

公开(公告)号：US11637181B2

公开(公告)日：2023-04-25

申请号：US17509327

申请日：2021-10-25

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Vibhor Jain ,  Alvin J. Joseph ,  Alexander Derrickson ,  Judson R. Holt ,  John J. Pekarik

IPC: H01L29/08 ,  H01L29/735 ,  H01L29/66 ,  H01L29/417

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to lateral bipolar transistors and methods of manufacture. The structure includes: an extrinsic base comprising semiconductor material; an intrinsic base comprising semiconductor material which is located below the extrinsic base; a polysilicon emitter on a first side of the extrinsic base; a raised collector on a second side of the extrinsic base; and sidewall spacers on the extrinsic base which separate the extrinsic base from the polysilicon emitter and the raised collector.

公开(公告)号：US20230064512A1

公开(公告)日：2023-03-02

申请号：US17456395

申请日：2021-11-24

Applicant: GlobalFoundries U.S. Inc.

Inventor： Vibhor Jain ,  John J. Pekarik ,  Alvin J. Joseph ,  Alexander M. Derrickson ,  Judson R. Holt

IPC: H01L29/735 ,  H01L29/08 ,  H01L29/15 ,  H01L29/10 ,  H01L29/66

Abstract: Embodiments of the disclosure provide a lateral bipolar transistor structure with a superlattice layer and methods to form the same. The bipolar transistor structure may have a semiconductor layer of a first single crystal semiconductor material over an insulator layer. The semiconductor layer includes an intrinsic base region having a first doping type. An emitter/collector (E/C) region may be adjacent the intrinsic base region and may have a second doping type opposite the first doping type. A superlattice layer is on the E/C region of the semiconductor layer. A raised E/C terminal, including a single crystal semiconductor material, is on the superlattice layer. The superlattice layer separates the E/C region from the raised E/C terminal.

公开(公告)号：US20220262930A1

公开(公告)日：2022-08-18

申请号：US17176251

申请日：2021-02-16

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Vibhor Jain ,  Judson R. Holt ,  Tayel Nesheiwat ,  John J. Pekarik ,  Christopher Durcan

IPC: H01L29/732 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66

Abstract: Device structures and fabrication methods for a bipolar junction transistor. The device structure includes a substrate and a trench isolation region in the substrate. The trench isolation region surrounds an active region of the substrate. The device structure further includes a collector in the active region of the substrate, a base layer having a first section positioned on the active region and a second section oriented at an angle relative to the first section, an emitter positioned on the first section of the base layer, and an extrinsic base layer positioned over the trench isolation region and adjacent to the emitter. The second section of the base layer is laterally positioned between the extrinsic base layer and the emitter.