公开(公告)号：US10978566B2

公开(公告)日：2021-04-13

申请号：US16742981

申请日：2020-01-15

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Hui Zang ,  Guowei Xu ,  Keith Tabakman ,  Viraj Sardesai

IPC: H01L29/66 ,  H01L29/417 ,  H01L21/28 ,  H01L21/311 ,  H01L21/768 ,  H01L27/088 ,  H01L21/8234

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to middle of line structures and methods of manufacture. The structure includes: a plurality of gate structures comprising source and/or drain metallization features; spacers on sidewalls of the gate structures and composed of a first material and a second material; and contacts in electrical contact with the source and/or drain metallization features, and separated from the gate structures by the spacers.

公开(公告)号：US10950692B2

公开(公告)日：2021-03-16

申请号：US16121058

申请日：2018-09-04

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Ruilong Xie ,  Vimal Kamineni ,  Shesh Mani Pandey ,  Hui Zang

IPC: H01L23/532 ,  H01L29/06 ,  H01L27/088 ,  H01L21/768 ,  H01L21/764 ,  H01L21/8234

Abstract: One device disclosed herein includes, among other things, first and second active regions, a first source/drain contact positioned above the first active region, a second source/drain contact positioned above the second active region, and a dielectric material disposed between the first and second source/drain contacts, wherein the dielectric material defines an air gap cavity positioned between the first and second source/drain contacts.

公开(公告)号：US12002869B2

公开(公告)日：2024-06-04

申请号：US17901887

申请日：2022-09-02

Applicant: GlobalFoundries U.S. Inc.

Inventor： Ruilong Xie ,  Youngtag Woo ,  Daniel Chanemougame ,  Bipul C. Paul ,  Lars W. Liebmann ,  Heimanu Niebojewski ,  Xuelian Zhu ,  Lei Sun ,  Hui Zang

IPC: H01L29/49 ,  H01L21/28 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/092 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/4975 ,  H01L21/28 ,  H01L21/823431 ,  H01L21/823475 ,  H01L27/0886 ,  H01L27/092 ,  H01L29/41775 ,  H01L29/66477 ,  H01L29/783

Abstract: One illustrative integrated circuit (IC) product disclosed herein includes a first conductive source/drain contact structure of a first transistor with an insulating source/drain cap positioned above at least a portion of an upper surface of the first conductive source/drain contact structure and a gate-to-source/drain (GSD) contact structure that is conductively coupled to the first conductive source/drain contact structure and a first gate structure of a second transistor. In this example, the product also includes a gate contact structure that is conductively coupled to a second gate structure of a third transistor, wherein an upper surface of each of the GSD contact structure and the gate contact structure is positioned at a first level that is at a level that is above a level of an upper surface of the insulating source/drain cap.

公开(公告)号：US11810812B2

公开(公告)日：2023-11-07

申请号：US17382645

申请日：2021-07-22

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Hui Zang ,  Ruilong Xie ,  Jessica M. Dechene

IPC: H01L21/762 ,  H01L29/66 ,  H01L21/308 ,  H01L27/088

CPC classification number: H01L21/76232 ,  H01L21/3086 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/66795

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to single diffusion cut for gate structures and methods of manufacture. The structure includes a single diffusion break extending into a substrate between diffusion regions of adjacent gate structures, the single diffusion break filled with an insulator material and further comprising an undercut region lined with a liner material which is between the insulator material and the diffusion regions.

公开(公告)号：US20220416054A1

公开(公告)日：2022-12-29

申请号：US17901887

申请日：2022-09-02

Applicant: GlobalFoundries U.S. Inc.

Inventor： Ruilong Xie ,  Youngtag Woo ,  Daniel Chanemougame ,  Bipul C. Paul ,  Lars W. Liebmann ,  Heimanu Niebojewski ,  Xuelian Zhu ,  Lei Sun ,  Hui Zang

IPC: H01L29/49 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L21/28 ,  H01L27/088 ,  H01L27/092

Abstract: One illustrative integrated circuit (IC) product disclosed herein includes a first conductive source/drain contact structure of a first transistor with an insulating source/drain cap positioned above at least a portion of an upper surface of the first conductive source/drain contact structure and a gate-to-source/drain (GSD) contact structure that is conductively coupled to the first conductive source/drain contact structure and a first gate structure of a second transistor. In this example, the product also includes a gate contact structure that is conductively coupled to a second gate structure of a third transistor, wherein an upper surface of each of the GSD contact structure and the gate contact structure is positioned at a first level that is at a level that is above a level of an upper surface of the insulating source/drain cap.

公开(公告)号：US11469309B2

公开(公告)日：2022-10-11

申请号：US16804264

申请日：2020-02-28

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Ruilong Xie ,  Youngtag Woo ,  Daniel Chanemougame ,  Bipul C. Paul ,  Lars W. Liebmann ,  Heimanu Niebojewski ,  Xuelian Zhu ,  Lei Sun ,  Hui Zang

IPC: H01L29/49 ,  H01L27/092 ,  H01L29/78 ,  H01L21/28 ,  H01L29/66 ,  H01L29/417 ,  H01L21/8234 ,  H01L27/088

Abstract: One illustrative integrated circuit (IC) product disclosed herein includes a first conductive source/drain contact structure of a first transistor with an insulating source/drain cap positioned above at least a portion of an upper surface of the first conductive source/drain contact structure and a gate-to-source/drain (GSD) contact structure that is conductively coupled to the first conductive source/drain contact structure and a first gate structure of a second transistor. In this example, the product also includes a gate contact structure that is conductively coupled to a second gate structure of a third transistor, wherein an upper surface of each of the GSD contact structure and the gate contact structure is positioned at a first level that is at a level that is above a level of an upper surface of the insulating source/drain cap.

公开(公告)号：US11450678B2

公开(公告)日：2022-09-20

申请号：US16683439

申请日：2019-11-14

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Hui Zang ,  Ruilong Xie ,  Shesh Mani Pandey

IPC: H01L29/423 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/51

Abstract: One illustrative integrated circuit (IC) product disclosed herein includes a selection gate electrode and a first gate insulation layer positioned above a substrate and a memory gate electrode positioned above the substrate and adjacent the selection gate electrode, wherein the memory gate electrode comprises a bottom surface and first and second opposing sidewall surfaces. This embodiment of the IC product also includes a plurality of layers of insulating material, wherein a first portion of the layers of insulating material is positioned between the first gate insulation layer and the first opposing sidewall of the memory gate electrode, a second portion of the layers of insulating material is positioned between the bottom surface of the memory gate electrode and the upper surface of the semiconductor substrate, and a third portion of the layers of insulating material is positioned on the second opposing sidewall of the conductive memory gate electrode.

公开(公告)号：US11450570B2

公开(公告)日：2022-09-20

申请号：US16367733

申请日：2019-03-28

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Hui Zang ,  Ruilong Xie

IPC: H01L21/8238 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/768 ,  H01L27/088 ,  H01L29/78

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a single diffusion cut for gate structures and methods of manufacture. The structure includes: a plurality of fin structures; a plurality of gate structures extending over the plurality of fin structures; a plurality of diffusion regions adjacent to the each of the plurality of gate structures; a single diffusion break between the diffusion regions of the adjacent gate structures; and a liner separating the single diffusion break from the diffusion regions.

公开(公告)号：US11114542B2

公开(公告)日：2021-09-07

申请号：US16441726

申请日：2019-06-14

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Hui Zang ,  Haigou Huang

IPC: H01L29/66 ,  H01L29/51 ,  H01L29/78 ,  H01L29/49 ,  H01L21/762

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to semiconductor device with reduced gate height budget and methods of manufacture. The method includes: forming a plurality of gate structures on a substrate; recessing material of the plurality of gate structures to below a surface of an insulator material; forming trenches in the insulator material and underlying material adjacent to sidewalls of the plurality of gate structures; and filling the recesses and trenches with a capping material.

公开(公告)号：US11031389B2

公开(公告)日：2021-06-08

申请号：US16436925

申请日：2019-06-11

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Jiehui Shu ,  Hui Zang

IPC: H01L27/06 ,  H01L27/105 ,  H01L21/8234 ,  H01L29/40 ,  H01L29/423 ,  H01L29/06

Abstract: The present disclosure generally relates to semiconductor devices and processing. The present disclosure also relates to semiconductor structures disposed over active regions, more particularly, via contact structures disposed over such active regions and to methods of forming such semiconductor structures.