公开(公告)号：US11437286B2

公开(公告)日：2022-09-06

申请号：US17012266

申请日：2020-09-04

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Hui Zang ,  Ruilong Xie

IPC: H01L29/08 ,  H01L29/417 ,  H01L27/088 ,  H01L29/165 ,  H01L21/8234 ,  H01L21/311 ,  H01L21/321 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/027

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to middle of line structures and methods of manufacture. The structure includes: a plurality of gate structures; source and drain regions adjacent to respective gate structures of the plurality of gate structures; metallization features contacting selected source and drain regions; and recessed metallization features contacting other selected source and drain regions.

公开(公告)号：US10923389B2

公开(公告)日：2021-02-16

申请号：US16288780

申请日：2019-02-28

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Chanro Park ,  Min Gyu Sung ,  Hoon Kim ,  Ruilong Xie

IPC: H01L29/78 ,  H01L21/768 ,  H01L29/66 ,  H01L29/06 ,  H01L29/49

Abstract: Structures for air-gap spacers in a field-effect transistor and methods for forming air-gap spacers in a field-effect transistor. A gate structure is formed on a top surface of a semiconductor body. A dielectric spacer is formed adjacent to a vertical sidewall of the gate structure. A semiconductor layer is formed on the top surface of the semiconductor body. The semiconductor layer is arranged relative to the vertical sidewall of the gate structure such that a first section of the first dielectric spacer is located in a space between the semiconductor layer and the vertical sidewall of the gate structure. A second section of the dielectric spacer that is located above a top surface of the semiconductor layer is removed. An air-gap spacer is formed in a space from which the second section of the dielectric spacer is removed.

公开(公告)号：US10903317B1

公开(公告)日：2021-01-26

申请号：US16534317

申请日：2019-08-07

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Julien Frougier ,  Ruilong Xie ,  Kangguo Cheng ,  Chanro Park

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78

Abstract: A gate-all-around field effect transistor (GAAFET) and method. The GAAFET includes nanosheets, a gate around center portions of the nanosheets, and inner spacers aligned below end portions. The nanosheet end portions are tapered from the source/drain regions to the gate and the inner spacers are tapered from the gate to the source/drain regions. Each inner spacer includes: a first spacer layer, which has a uniform thickness and extends laterally from the gate to an adjacent source/drain region; a second spacer layer, which fills the space between a planar top surface of the first spacer layer and a tapered end portion of the nanosheet above; and, for all but the lowermost inner spacers, a third spacer layer, which is the same material as the second spacer layer and which fills the space between a planar bottom surface of the first spacer layer and a tapered end portion of the nanosheet below.

公开(公告)号：US11923248B2

公开(公告)日：2024-03-05

申请号：US17861450

申请日：2022-07-11

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Hui Zang ,  Ruilong Xie

IPC: H01L21/8238 ,  H01L21/768 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823437 ,  H01L21/76831 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a single diffusion cut for gate structures and methods of manufacture. The structure includes: a plurality of fin structures; a plurality of gate structures extending over the plurality of fin structures; a plurality of diffusion regions adjacent to the each of the plurality of gate structures; a single diffusion break between the diffusion regions of the adjacent gate structures; and a liner separating the single diffusion break from the diffusion regions.

公开(公告)号：US11127623B2

公开(公告)日：2021-09-21

申请号：US16213189

申请日：2018-12-07

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Hui Zang ,  Ruilong Xie ,  Jessica M. Dechene

IPC: H01L21/308 ,  H01L21/762 ,  H01L29/66 ,  H01L27/088

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to single diffusion cut for gate structures and methods of manufacture. The structure includes a single diffusion break extending into a substrate between diffusion regions of adjacent gate structures, the single diffusion break filled with an insulator material and further comprising an undercut region lined with a liner material which is between the insulator material and the diffusion regions.

公开(公告)号：US10950692B2

公开(公告)日：2021-03-16

申请号：US16121058

申请日：2018-09-04

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Ruilong Xie ,  Vimal Kamineni ,  Shesh Mani Pandey ,  Hui Zang

IPC: H01L23/532 ,  H01L29/06 ,  H01L27/088 ,  H01L21/768 ,  H01L21/764 ,  H01L21/8234

Abstract: One device disclosed herein includes, among other things, first and second active regions, a first source/drain contact positioned above the first active region, a second source/drain contact positioned above the second active region, and a dielectric material disposed between the first and second source/drain contacts, wherein the dielectric material defines an air gap cavity positioned between the first and second source/drain contacts.

公开(公告)号：US10916478B2

公开(公告)日：2021-02-09

申请号：US15899508

申请日：2018-02-20

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Lei L. Zhuang ,  Balasubramanian Pranatharthiharan ,  Lars Liebmann ,  Ruilong Xie ,  Terence Hook

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/78 ,  H01L27/11

Abstract: In a self-aligned fin cut process for fabricating integrated circuits, a sacrificial gate or an epitaxially-formed source/drain region is used as an etch mask in conjunction with a fin cut etch step to remove unwanted portions of the fins. The process eliminates use of a lithographically-defined etch mask to cut the fins, which enables precise and accurate alignment of the fin cut.

公开(公告)号：US20230395502A1

公开(公告)日：2023-12-07

申请号：US18362044

申请日：2023-07-31

Applicant: GlobalFoundries U.S. Inc.

Inventor： Ruilong Xie ,  Lars Liebmann ,  Daniel Chanemougame ,  Geng Han

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5283 ,  H01L23/5226 ,  H01L21/76802 ,  H01L21/76816 ,  H01L23/53295 ,  H01L21/76879 ,  H01L21/02164

Abstract: An integrated circuit product includes a first layer of insulating material above a device layer of a semiconductor substrate and with a lowermost surface above an uppermost surface of a gate of a transistor in a device layer of the semiconductor substrate. A metallization blocking structure is in an opening in the first layer of insulating material and has a lowermost surface above the uppermost surface of the gate and includes a second insulating material that is different from the first insulating material. A metallization trench is in the first layer of insulating material on opposite sides of the metallization blocking structure. A contact structure is in the second insulating material and entirely below the metallization trench. A conductive metallization line includes first and second portions positioned in the metallization trench on opposite sides of the metallization blocking structure and a long axis extending along the first and second portions.

公开(公告)号：US11621333B2

公开(公告)日：2023-04-04

申请号：US16555734

申请日：2019-08-29

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Ruilong Xie ,  Hao Tang ,  Cheng Chi ,  Daniel Chanemougame ,  Lars W. Liebmann ,  Mark V. Raymond

IPC: H01L29/417 ,  H01L21/768 ,  H01L29/66 ,  H01L21/285 ,  H01L23/535 ,  H01L29/78 ,  H01L29/45 ,  H01L27/092 ,  H01L29/08 ,  H01L21/8238

Abstract: One illustrative transistor device disclosed herein includes, among other things, a gate positioned above a semiconductor substrate, the gate comprising a gate structure, a conductive source/drain metallization structure positioned adjacent the gate, the conductive source/drain metallization structure having a front face, and an insulating spacer that is positioned on and in contact with at least a portion of the front face of the conductive source/drain metallization structure. In this example, the device also includes a gate contact opening that exposes at least a portion of the insulating spacer and a portion of an upper surface of the gate structure and a conductive gate contact structure positioned in the gate contact opening, wherein the conductive gate contact structure contacts at least a portion of the insulating spacer and wherein the conductive gate contact structure is conductively coupled to the gate structure.

公开(公告)号：US11621269B2

公开(公告)日：2023-04-04

申请号：US16298413

申请日：2019-03-11

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Julien Frougier ,  Ruilong Xie

IPC: H01L27/11514 ,  H01L27/11502 ,  H01L23/522 ,  H01L49/02

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a multi-level ferroelectric memory cell and methods of manufacture. The structure includes: a first metallization feature; a tapered ferroelectric capacitor comprising a first electrode, a second electrode and ferroelectric material between the first electrode and the second electrode, the first electrode contacting the first metallization feature; and a second metallization feature contacting the second electrode.