公开(公告)号：US11004748B2

公开(公告)日：2021-05-11

申请号：US16432899

申请日：2019-06-05

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Sipeng Gu ,  Jiehui Shu ,  Haiting Wang

IPC: H01L21/8234 ,  H01L29/423 ,  H01L29/10 ,  H01L27/088

Abstract: This disclosure relates to a method of fabricating semiconductor devices with a gate-to-gate spacing that is wider than a minimum gate-to-gate spacing and the resulting semiconductor devices. The method includes forming gate structures over an active structure, the gate structures including a first gate structure, a second gate structure, and a third gate structure. The second gate structure is between the first and third gate structures. A plurality of epitaxial structures are formed adjacent to the gate structures, wherein the second gate structure separates two epitaxial structures and the two epitaxial structures are between the first and third gate structures. The second gate structure is removed. A conductive region is formed to connect the epitaxial structures between the first and third gate structures.

公开(公告)号：US20210125984A1

公开(公告)日：2021-04-29

申请号：US16660868

申请日：2019-10-23

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Judson R. Holt ,  Jiehui Shu

IPC: H01L27/092 ,  H01L21/8238

Abstract: A method limits lateral epitaxy growth at an N-P boundary area using an inner spacer. The method may include forming inner spacers on inner sidewalls of the inner active regions of a first polarity region (e.g., n-type) and an adjacent second polarity region (e.g., p-type) that are taller than any outer spacers on an outer sidewall of the inner active regions. During forming of semiconductor layers over the active regions (e.g., via epitaxy), the inner spacers abut and limit lateral forming of the semiconductor layer. The method generates larger semiconductor layers than possible with conventional approaches, and prevents electrical shorts between the semiconductor layers in an N-P boundary area. A structure includes the semiconductor epitaxy layers separated from one another, and abutting respective inner spacers. Any outer spacer on the inner active region is shorter than a respective inner spacer.

公开(公告)号：US10943814B1

公开(公告)日：2021-03-09

申请号：US16547474

申请日：2019-08-21

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Ryan W. Sporer ,  Jiehui Shu

IPC: H01L21/762 ,  H01L29/06 ,  H01L21/768 ,  H01L21/74

Abstract: A method forms a trench isolation opening extending into an SOI substrate, and forms an etch stop member in a portion of the insulator layer abutting a side of the trench isolation opening. The etch stop member has a higher etch selectivity than the insulator layer of the SOI substrate. A trench isolation is formed in the trench isolation opening. A contact is formed to a portion of the semiconductor layer of the SOI substrate. The etch stop member is structured to prevent contact punch through to the base substrate of the SOI substrate.

公开(公告)号：US11721728B2

公开(公告)日：2023-08-08

申请号：US16777531

申请日：2020-01-30

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Sipeng Gu ,  Jiehui Shu ,  Halting Wang ,  Yanping Shen

IPC: H01L29/417 ,  H01L29/78

CPC classification number: H01L29/41775 ,  H01L29/41791 ,  H01L29/7851

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to self-aligned contacts and methods of manufacture. The structure includes: adjacent diffusion regions located within a substrate material; sidewall structures above an upper surface of the substrate material, aligned on sides of the adjacent diffusion regions; and a contact between the sidewall structures and extending to within the substrate material between and in electrical contact with the adjacent diffusion regions.

公开(公告)号：US11482456B2

公开(公告)日：2022-10-25

申请号：US16360183

申请日：2019-03-21

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Yanping Shen ,  Hui Zang ,  Jiehui Shu

IPC: H01L21/8234 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/02 ,  H01L27/088 ,  H01L29/49 ,  H01L29/423

Abstract: A method of forming an IC structure includes providing a metal gate structure, a spacer adjacent the metal gate structure and a contact to each of a pair of source/drain regions adjacent sides of the spacer. The spacer includes a first dielectric having a first dielectric constant. The metal gate structure is recessed, and the spacer is recessed to have an upper surface of the first dielectric below an upper surface of the metal gate structure, leaving a lower spacer portion. An upper spacer portion of a second dielectric having a dielectric constant lower than the first dielectric is formed over the lower spacer portion. A gate cap is formed over the metal gate structure and the upper spacer portion. The second dielectric can include, for example, an oxide or a gas. The method may reduce effective capacitance and gate height loss, and improve gate-to-contact short margin.

公开(公告)号：US11217584B2

公开(公告)日：2022-01-04

申请号：US16660868

申请日：2019-10-23

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Judson R. Holt ,  Jiehui Shu

IPC: H01L27/092 ,  H01L21/8238 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/84 ,  H01L27/12 ,  H01L29/417 ,  H01L21/82 ,  H01L29/66

Abstract: A method limits lateral epitaxy growth at an N-P boundary area using an inner spacer. The method may include forming inner spacers on inner sidewalls of the inner active regions of a first polarity region (e.g., n-type) and an adjacent second polarity region (e.g., p-type) that are taller than any outer spacers on an outer sidewall of the inner active regions. During forming of semiconductor layers over the active regions (e.g., via epitaxy), the inner spacers abut and limit lateral forming of the semiconductor layers. The method generates larger semiconductor layers than possible with conventional approaches, and prevents electrical shorts between the semiconductor layers in an N-P boundary area. A structure includes the semiconductor epitaxy layers separated from one another, and abutting respective inner spacers. Any outer spacer on the inner active region is shorter than a respective inner spacer.

公开(公告)号：US20210249508A1

公开(公告)日：2021-08-12

申请号：US17243832

申请日：2021-04-29

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Jiehui Shu ,  Baofu Zhu ,  Haiting Wang ,  Sipeng Gu

IPC: H01L29/08 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/66

Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A gate structure is arranged over a channel region of a semiconductor body. A first source/drain region is coupled to a first portion of the semiconductor body, and a second source/drain region is located in a second portion the semiconductor body. The first source/drain region includes an epitaxial semiconductor layer containing a first concentration of a dopant. The second source/drain region contains a second concentration of the dopant. The channel region is positioned in the semiconductor body between the first source/drain region and the second source/drain region.

公开(公告)号：US20210242344A1

公开(公告)日：2021-08-05

申请号：US16781236

申请日：2020-02-04

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Haiting Wang ,  Sipeng Gu ,  Jiehui Shu ,  Baofu Zhu

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08

Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A gate structure extends over a channel region in a semiconductor body. The gate structure has a first side surface and a second side surface opposite the first side surface. A first source/drain region is positioned adjacent to the first side surface of the gate structure and a second source/drain region is positioned adjacent to the second side surface of the gate structure. The first source/drain region includes a first epitaxial semiconductor layer, and the second source/drain region includes a second epitaxial semiconductor layer. A first top surface of the first epitaxial semiconductor layer is positioned at a first distance from the channel region, a second top surface of the second epitaxial semiconductor layer is positioned at a second distance from the channel region, and the first distance is greater than the second distance.

公开(公告)号：US11075268B2

公开(公告)日：2021-07-27

申请号：US16541600

申请日：2019-08-15

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Jiehui Shu ,  Baofu Zhu ,  Haiting Wang ,  Sipeng Gu

IPC: H01L29/08 ,  H01L29/66 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/78

Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A gate structure is arranged over a channel region of a semiconductor body. A first source/drain region is coupled to a first portion of the semiconductor body, and a second source/drain region is located in a second portion the semiconductor body. The first source/drain region includes an epitaxial semiconductor layer containing a first concentration of a dopant. The second source/drain region contains a second concentration of the dopant. The channel region is positioned in the semiconductor body between the first source/drain region and the second source/drain region.

公开(公告)号：US11043566B2

公开(公告)日：2021-06-22

申请号：US16599116

申请日：2019-10-10

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Jiehui Shu ,  Judson Robert Holt ,  Sipeng Gu ,  Haiting Wang

IPC: H01L29/423 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/417

Abstract: A semiconductor device is provided that includes a substrate, an active region, a pair of gates, a plurality of semiconductor structures and a plurality of pillar structures. The active region is over the substrate. The pair of gates is formed over the active region, and each gate of the pair of gates includes a gate structure and a pair of spacer structures disposed on sidewalls of the gate structure. The plurality of semiconductor structures is arranged between the pair of gates in an alternating arrangement configuration having a first width and a second width. The first width is substantially equal to a width of the gate structure. The plurality of semiconductor structures is separated by the plurality of pillar structures.