公开(公告)号：US20060007757A1

公开(公告)日：2006-01-12

申请号：US10886428

申请日：2004-07-07

申请人： Sugato Mukherjee ,  Wen Li ,  Christopher Morzano

发明人： Sugato Mukherjee ,  Wen Li ,  Christopher Morzano

IPC分类号： G11C7/00

CPC分类号： G11C7/1087 ,  G11C7/1078 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222

摘要： The disclosed system and method significantly reduce or eliminate DQS postamble ringing problem in modern high-speed memory chips, allowing the memory chips to be operated at significantly faster clock speeds. The external strobe signal (XDQS) may be used to generate at least two derivative strobe signals therefrom. Instead of the XDQS signal, the derivative strobe signals are then used, in a predetermined order, to clock in or strobe the data to be written into memory cells. The last generated derivative strobe signal may be used to finally transfer the data bits into memory cells. Once the last of the derivative strobe signals is activated, and so long as there are no more data writes pending in the command pipe for the next clock cycle, the rising or falling edge of the last derivative strobe signal can be detected to turn off further generation of the strobe signals prior to any onset of postamble ringing on the XDQS signal. Thus, false data may not get “clocked in” or written into the memory chip because of postamble ringing. This prevents data corruption and preserves the integrity of the data written into a memory chip.

公开(公告)号：US20070097781A1

公开(公告)日：2007-05-03

申请号：US11640983

申请日：2006-12-19

申请人： Wen Li ,  Christopher Morzano

发明人： Wen Li ,  Christopher Morzano

IPC分类号： G11C8/00

CPC分类号： G11C7/1078 ,  G11C7/02 ,  G11C7/1006 ,  G11C7/1066 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/1096 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4096 ,  G11C2207/107 ,  G11C2207/2254

摘要： A calibration circuit for calibrating the input data path of a digital circuit is disclosed. A simple string of a repeating data pattern such as, e.g., “1100,” is sent on the data path. The digital circuit captures the data using a clock signal, examines the data signal for the predetermined pattern and adjusts a delay applied to the data signal until the predetermined pattern is recognized. Then the delay is further adjusted until the predetermined pattern is no longer recognized indicating that an edge of the eye of the data is near a clocking edge of the clocking signal. The delay applied to the data signal is then further adjusted by a predetermined amount to position the clock edge near the center of the data eye.

公开(公告)号：US20070046511A1

公开(公告)日：2007-03-01

申请号：US11218997

申请日：2005-09-01

申请人： Christopher Morzano ,  Wen Li

发明人： Christopher Morzano ,  Wen Li

IPC分类号： H03M9/00

CPC分类号： G11C7/1051 ,  G11C7/10 ,  G11C7/1012 ,  G11C2207/107 ,  H03M9/00

摘要： A method and apparatus to convert parallel data to serial data. More specifically, there is provided a parallel-to-serial converter comprising a data pipeline configured to receive parallel data, and binary sort logic comprising a plurality of switches arranged to receive the parallel data from the data pipeline, and configured to output the parallel data serially.

摘要翻译： 将并行数据转换为串行数据的方法和装置。 更具体地，提供了一种并行 - 串行转换器，其包括被配置为接收并行数据的数据流水线，以及二进制排序逻辑，其包括多个开关，其被布置为从数据流水线接收并行数据，并且被配置为输出并行数据 连续地

公开(公告)号：US20060187740A1

公开(公告)日：2006-08-24

申请号：US11061035

申请日：2005-02-18

申请人： Jeffrey Janzen ,  Christopher Morzano

发明人： Jeffrey Janzen ,  Christopher Morzano

IPC分类号： G11C8/00

CPC分类号： G11C7/1045 ,  G11C7/1048 ,  G11C11/4096

摘要： A DRAM device includes a mode register that is programmed to select one of two modes for operating data bus terminals in the device. A timing circuit generates timing signals in synchronism with the clock signal that correspond to the selected mode. The timing signals are combined with read data signals to generate corresponding timed read data signals. These timed data signals and termination signals from the timing circuit are applied to pull-up and pull-down circuitry, which drive respective pull-up and pull-down transistors coupled to the data bus terminals. The transistors drive the data bus terminals to either a first or a second voltage if the first mode of operation is selected and to either a third or a fourth voltage if the second mode of operation is selected. Additionally, the pull-up and pull-down transistors bias the data bus terminals to respective voltages corresponding to the selected operating mode.

摘要翻译： DRAM设备包括被编程为选择用于在设备中操作数据总线端子的两种模式之一的模式寄存器。 定时电路产生与对应于所选模式的时钟信号同步的定时信号。 定时信号与读数据信号组合，以产生相应的定时读数据信号。 来自定时电路的这些定时数据信号和终止信号被施加到上拉和下拉电路，其驱动耦合到数据总线端子的相应上拉和下拉晶体管。 如果选择了第一操作模式，则晶体管将数据总线端子驱动为第一或第二电压，并且如果选择了第二操作模式，则晶体管驱动到第三或第四电压。 此外，上拉和下拉晶体管将数据总线端子偏置到对应于所选择的操作模式的相应电压。

公开(公告)号：US20060013060A1

公开(公告)日：2006-01-19

申请号：US10894269

申请日：2004-07-19

申请人： Wen Li ,  Christopher Morzano

发明人： Wen Li ,  Christopher Morzano

IPC分类号： G11C8/00

CPC分类号： G11C8/10 ,  G11C7/1078 ,  G11C7/1093

摘要： Disclosed herein are exemplary embodiments of an improved write address shift register structure useful for example in a DDR3 DRAM having read/write latency. The disclosed shift register structure propagates write addresses from an address bus outside the device to array decoders to allow latent data to be written into the cells in the memory array at a proper time. The register structure comprises a reduced number of registers (e.g., four) thus eliminating the need for extraneous registers which might otherwise be used to propagate “don't care” addresses. The registers are clocked, and the addresses propagated though the registers, in accordance with a latency bus through which a user defines the desired read/write latency in accordance with user preferences and the desired clock speed of the device. The clock for each register is preferably decoded from the latency bus and hence each register preferably has its own unique clock.

摘要翻译： 这里公开了改进的写地址移位寄存器结构的示例性实施例，例如在具有读/写延迟的DDR3 DRAM中有用。 所公开的移位寄存器结构将写入地址从设备外部的地址总线传播到阵列解码器，以允许在适当的时间将潜在数据写入存储器阵列中的单元。 寄存器结构包括减少数量的寄存器（例如，四个寄存器），因此消除了对外部寄存器的需要，否则这些寄存器可能用于传播“无关心”地址。 根据用户根据用户偏好和设备的期望时钟速度定义所需读/写延迟的等待时间总线，寄存器被计时，并且通过寄存器传播的地址。 每个寄存器的时钟优选地从等待时间总线解码，因此每个寄存器优选地具有其自己的唯一时钟。

公开(公告)号：US20070121416A1

公开(公告)日：2007-05-31

申请号：US11698467

申请日：2007-01-26

申请人： Christopher Morzano ,  Jeffrey Wright

发明人： Christopher Morzano ,  Jeffrey Wright

IPC分类号： G11C8/00

CPC分类号： G11C8/10 ,  G11C11/4087 ,  G11C29/844

摘要： An apparatus and method for selecting a storage location in a memory device including receiving at least one of a pre-decoded location address signal, a match signal, and a redundant location address enable signal, enabling one of a decoder and a redundant decoder in response to the match signal, wherein the decoder is operable to generate a location select signal for selecting a first location, the decoder being responsive to the pre-decoded location address signal, and wherein the redundant decoder is operable to generate a redundant location select signal for selecting a second location, the redundant decoder being responsive to the redundant location address enable signal, and terminating one of the generation of a location select signal and the generation of a redundant location select signal in response to a precharge signal.

摘要翻译： 一种用于选择存储设备中的存储位置的装置和方法，包括接收预解码位置地址信号，匹配信号和冗余位置地址使能信号中的至少一个，使解码器和冗余解码器之一响应 其中所述解码器可操作以产生用于选择第一位置的位置选择信号，所述解码器响应于所述预解码的位置地址信号，并且其中所述冗余解码器可操作以产生用于 选择第二位置，所述冗余解码器响应于所述冗余位置地址使能信号，并且终止所述产生位置选择信号和响应于预充电信号产生冗余位置选择信号。

公开(公告)号：US20050254336A1

公开(公告)日：2005-11-17

申请号：US11187058

申请日：2005-07-22

申请人： Christopher Morzano ,  Wen Li

发明人： Christopher Morzano ,  Wen Li

IPC分类号： G11C7/10 ,  G11C7/22 ,  G11C8/00 ,  G11C11/4076 ,  G11C11/4094

CPC分类号： G11C7/22 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1093 ,  G11C11/4076 ,  G11C11/4094

摘要： A data strobe synchronization circuit includes first and second logic circuits receiving global data strobe pulses and respective enable signal. A control circuit initially applies an enable signal to the first logic circuit so that the first logic circuit generates a first data strobe pulse responsive to each global data strobe pulse. The control circuit receives a write control signal. When the write control signal becomes active, the control circuit terminates the enable signal applied to the first logic circuit and applies an enable signal to the second logic circuit. The second logic circuit then generates a second data strobe pulse responsive to the next global data strobe pulse. The first and second data strobe pulses are used to latch a data signal in respective flip-flops. The data strobe pulses may latch the data signal in pairs of flip-flops on the leading and trailing edges of the data strobe pulses.

摘要翻译： 数据选通同步电路包括接收全局数据选通脉冲的第一和第二逻辑电路和相应的使能信号。 控制电路首先向第一逻辑电路施加使能信号，使得第一逻辑电路响应于每个全局数据选通脉冲产生第一数据选通脉冲。 控制电路接收写入控制信号。 当写入控制信号变为有效时，控制电路终止施加到第一逻辑电路的使能信号并向第二逻辑电路施加使能信号。 然后，第二逻辑电路响应于下一个全局数据选通脉冲产生第二数据选通脉冲。 第一和第二数据选通脉冲用于锁存相应触发器中的数据信号。 数据选通脉冲可以在数据选通脉冲的前沿和后沿成对的触发器锁存数据信号。

公开(公告)号：US20050007836A1

公开(公告)日：2005-01-13

申请号：US10617246

申请日：2003-07-09

申请人： Christopher Morzano ,  Wen Li

发明人： Christopher Morzano ,  Wen Li

IPC分类号： G11C7/10 ,  G11C7/22 ,  G11C8/00 ,  G11C11/4076 ,  G11C11/4094 ,  G11C7/00

CPC分类号： G11C7/22 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1093 ,  G11C11/4076 ,  G11C11/4094

摘要： A data strobe synchronization circuit includes first and second logic circuits receiving global data strobe pulses and respective enable signal. A control circuit initially applies an enable signal to the first logic circuit so that the first logic circuit generates a first data strobe pulse responsive to each global data strobe pulse. The control circuit receives a write control signal. When the write control signal becomes active, the control circuit terminates the enable signal applied to the first logic circuit and applies an enable signal to the second logic circuit. The second logic circuit then generates a second data strobe pulse responsive to the next global data strobe pulse. The first and second data strobe pulses are used to latch a data signal in respective flip-flops. The data strobe pulses may latch the data signal in pairs of flip-flops on the leading and trailing edges of the data strobe pulses.

摘要翻译： 数据选通同步电路包括接收全局数据选通脉冲的第一和第二逻辑电路和相应的使能信号。 控制电路首先向第一逻辑电路施加使能信号，使得第一逻辑电路响应于每个全局数据选通脉冲产生第一数据选通脉冲。 控制电路接收写入控制信号。 当写入控制信号变为有效时，控制电路终止施加到第一逻辑电路的使能信号并向第二逻辑电路施加使能信号。 然后，第二逻辑电路响应于下一个全局数据选通脉冲产生第二数据选通脉冲。 第一和第二数据选通脉冲用于锁存相应触发器中的数据信号。 数据选通脉冲可以在数据选通脉冲的前沿和后沿成对的触发器锁存数据信号。

公开(公告)号：US5886940A

公开(公告)日：1999-03-23

申请号：US916835

申请日：1997-08-21

申请人： Christopher Morzano ,  Wen Li

发明人： Christopher Morzano ,  Wen Li

IPC分类号： G11C8/00

CPC分类号： G11C8/12 ,  G11C17/18 ,  G11C29/785

摘要： A circuit is provided for programming antifuses while preventing other antifuses from being inadvertently programmed or stressed. The antifuses and programming circuits are arranged in a plurality of banks, each of which contains a plurality of programming circuits corresponding in number to the number of bits of an address signal. The bits of the address signal are applied to corresponding programming circuits in all of the banks. The programming circuits each include a antifuse select transistor coupling its respective antifuse to a bank select node for the bank. The antifuses in one of the banks are programmed by coupling the bank select node for that bank to ground through a bank select transistor. The antifuse select transistor in the programming circuit and the bank select transistor thus complete a current path from a programming node, through the antifuse and transistors to ground. However, the interconnection of the bank select transistor and the antifuse select transistor has a relatively high parasitic capacitance. As a result, significant current can be capacitively coupled through the bank select transistor of the nonselected bank, thereby inadvertently programming the antifuses in the nonselected bank. Inadvertent programming of antifuses in the nonselected bank is avoided by charging the parasitic capacitances of the bank select nodes in the nonselected banks. As a result, the antifuse select transistors in each of the programming circuits are maintained in an OFF condition, and the voltage across the parasitic capacitances remains relatively constant, thereby limiting the current flowing through the parasitic capacitances.

摘要翻译： 提供了用于编程反熔丝的电路，同时防止其他反熔丝被无意编程或应力。 反熔丝和编程电路布置在多个存储体中，每个存储体中包含多个对应于地址信号的位数的编程电路。 地址信号的位被施加到所有存储体中的对应的编程电路。 编程电路各自包括将其相应反熔丝耦合到银行的存储体选择节点的反熔丝选择晶体管。 通过通过bank选择晶体管将该组的存储体选择节点耦合到地来编程一个存储体中的反熔丝。 因此，编程电路中的反熔丝选择晶体管和存储体选择晶体管完成从编程节点通过反熔丝和晶体管到地的电流路径。 然而，存储体选择晶体管和反熔丝选择晶体管的互连具有较高的寄生电容。 结果，可以通过非选择存储体的存储体选择晶体管电容耦合有效电流，从而无意地编程非选择存储体中的反熔丝。 通过对非选择的组中的存储体选择节点的寄生电容进行充电来避免非选择存储体中的反熔丝的无意编程。 结果，每个编程电路中的反熔丝选择晶体管保持在OFF状态，并且寄生电容两端的电压保持相对恒定，从而限制流过寄生电容的电流。