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公开(公告)号：US5416439A
公开(公告)日：1995-05-16
申请号：US174065
申请日：1993-12-28
申请人： Guoliang Shou , Weikang Yang , Sunao Takatori , Makoto Yamamoto
发明人： Guoliang Shou , Weikang Yang , Sunao Takatori , Makoto Yamamoto
CPC分类号： G06J1/00
摘要： An analog calculating circuit capable of storing data.A calculating circuit according to the present invention converts an analog voltage level to a time value by using a charging voltage of an RC circuit and stores the time value as a number of clock cycles in a digital counter. The circuit then converts another voltage level to a second time value and either adds the second time value to or subtracts it from the first time value. This yields a time value corresponding to a multiplication or division, respectively, of the analog voltage levels.
摘要翻译： 一种能够存储数据的模拟计算电路。 根据本发明的计算电路通过使用RC电路的充电电压将模拟电压电平转换为时间值，并将时间值作为时钟周期数存储在数字计数器中。 然后，电路将另一电压电平转换为第二时间值，并将第二时间值与第一时间值相加或相减。 这产生分别对应于模拟电压电平的乘法或除法的时间值。
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公开(公告)号：US5381375A
公开(公告)日：1995-01-10
申请号：US137736
申请日：1993-10-19
申请人： Guoliang Shou , Weikang Yang , Sunao Takatori , Makoto Yamamoto
发明人： Guoliang Shou , Weikang Yang , Sunao Takatori , Makoto Yamamoto
CPC分类号： G11C27/024 , G11C27/005
摘要： A memory device capable of storing a time element. The memory device includes: i) a threshold element outputting a voltage output when a gate voltage reaches a threshold voltage; ii) two inputs capacitive coupling connected to a gate of the threshold element; iii) the first RC circuit connected to the first input of the two inputs capacitive coupling; iv) the first RC circuit charging capacitance by the constant number in the predetermined time through the predetermined reference voltage inputs; v) the charging voltage of the capacitance inputted into the two inputs capacitive coupling, and vi) an output of the threshold element connected to a memory element whose parameter is time.
摘要翻译： 一种能够存储时间元素的存储器件。 存储器件包括：i）当栅极电压达到阈值电压时，输出电压输出的阈值元件; ii）连接到阈值元件的栅极的两个输入电容耦合; iii）第一个RC电路连接到两个输入的第一个输入电容耦合; iv）通过预定的参考电压输入，在预定时间内通过恒定数量的第一RC电路充电电容; v）输入到两个输入电容耦合的电容的充电电压，以及vi）连接到参数为时间的存储元件的阈值元件的输出。
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公开(公告)号：US5361219A
公开(公告)日：1994-11-01
申请号：US158295
申请日：1993-11-29
申请人： Guoliang Shou , Weikang Yang , Sunao Takatori , Makoto Yamamoto
发明人： Guoliang Shou , Weikang Yang , Sunao Takatori , Makoto Yamamoto
IPC分类号： G06J1/00
CPC分类号： G06J1/00
摘要： A multiplication circuit for directly multiplying analog and digital data without converting the analog data into digital data or the digital data into analog data. The multiplication circuit controls an analog input voltage by the use of a switching signal of a digital voltage so as to generate an analog output or to cut-off the output. Digital input signals b.sub.0 to b.sub.7 corresponding to a plural number of bits are integrated and given corresponding weights by use of a capacitive coupling unit, and a sign bit is added by the capacitive coupling unit by giving the sign bit double the weight of the most significant bit of the digital input.
摘要翻译： 一个乘法电路，用于直接将模拟和数字数字相乘而不将模拟数据转换为数字数据或将数字数据转换为模拟数据。 乘法电路通过使用数字电压的开关信号来控制模拟输入电压，以产生模拟输出或截止输出。 通过使用电容耦合单元将对应于多个位的数字输入信号b0至b7积分并给出相应的权重，并且通过给符号位加上最高有效位权重的符号位，由电容耦合单元加上符号位 位的数字输入。
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公开(公告)号：US5469102A
公开(公告)日：1995-11-21
申请号：US196837
申请日：1994-02-15
申请人： Guoliang Shou , Weikang Yang , Sunao Takatori , Makoto Yamamoto
发明人： Guoliang Shou , Weikang Yang , Sunao Takatori , Makoto Yamamoto
CPC分类号： G06G7/14
摘要： A summing circuit for executing summing of analog data with sign. The summing circuit includes two serially connected inverters INV1 and INV2, each having a feed back line, and selectively inputs data D1 to D8 to one of the first or the second stages, corresponding to positive/negative sign signals S1 to S8.
摘要翻译： 用于执行模拟数据与符号相加的求和电路。 求和电路包括两个串联的反相器INV1和INV2，每个具有反馈线，并且对应于正/负号信号S1至S8，选择性地将数据D1至D8输入到第一或第二级中的一个。
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公开(公告)号：US5406131A
公开(公告)日：1995-04-11
申请号：US174064
申请日：1993-12-28
申请人： Guoliang Shou , Weikang Yang , Sunao Takatori , Makoto Yamamoto
发明人： Guoliang Shou , Weikang Yang , Sunao Takatori , Makoto Yamamoto
CPC分类号： G04F10/10
摘要： An exponential circuit according to the present invention converts voltage level to time by using a charged voltage of RC circuit RC.sub.1, registers time as a clock number at a digital counter and performs bit shift for the registered data.
摘要翻译： 根据本发明的指数电路通过使用RC电路RC1的充电电压将电压电平转换为时间，在数字计数器处将时间作为时钟数进行登记，并对登记的数据执行位移。
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公开(公告)号：US5500810A
公开(公告)日：1996-03-19
申请号：US231766
申请日：1994-04-25
申请人： Guoliang Shou , Weikang Yang , Sunao Takatori , Makoto Yamamoto
发明人： Guoliang Shou , Weikang Yang , Sunao Takatori , Makoto Yamamoto
CPC分类号： H03H17/0291 , H03H15/00
摘要： A filter device with memory test circuit easily executes a memory test inspite of single-bit data processing to 1 bit data. The filter device with a memory test circuit includes a memory test circuit between a memory means and a shift register, sequentially reads digital data and tests digital data at the external Central Processing Unit (CPU) after converting the data from parallel to serial at the shift register.
摘要翻译： 具有存储器测试电路的滤波器器件容易地执行单位数据处理到1位数据的存储器测试。 具有存储器测试电路的滤波器装置包括存储器装置和移位寄存器之间的存储器测试电路，在将数据从并行转换为串行数据之后顺序读取数字数据并在外部中央处理器（CPU）测试数字数据 寄存器。
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公开(公告)号：US5452336A
公开(公告)日：1995-09-19
申请号：US151030
申请日：1993-11-12
申请人： Guoliang Shou , Weikang Yang , Sunao Takatori , Makoto Yamamoto
发明人： Guoliang Shou , Weikang Yang , Sunao Takatori , Makoto Yamamoto
摘要： A memory device for recording a time factor of data includes a threshold element, coupling capacitance, an RC-circuit, and a digital counter. A reference voltage is input to the RC-circuit. The output of the RC-circuit and an input voltage are each input to the coupling capacitance. The output of the coupling capacitance is input to the threshold element. When the voltage received by the threshold element reaches a threshold voltage level, the threshold element generates an output voltage. The digital counter receives the threshold element output voltage and the reference voltage. The digital counter is triggered by the reference voltage to begin counting clock pulses generated by a reference clock. The digital counter is then triggered by the threshold element output voltage to stop counting the clock pulses.
摘要翻译： 用于记录数据的时间因子的存储器件包括阈值元件，耦合电容，RC电路和数字计数器。 参考电压被输入到RC电路。 RC电路的输出和输入电压各自输入到耦合电容。 耦合电容的输出被输入到阈值元件。 当由阈值元件接收的电压达到阈值电压电平时，阈值元件产生输出电压。 数字计数器接收阈值元件输出电压和参考电压。 数字计数器由参考电压触发，开始计数由参考时钟产生的时钟脉冲。 数字计数器然后由阈值元件输出电压触发，以停止对时钟脉冲的计数。
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公开(公告)号：US5424965A
公开(公告)日：1995-06-13
申请号：US172393
申请日：1993-12-23
申请人： Guoliang Shou , Weikang Yang , Sunao Takatori , Makoto Yamamoto
发明人： Guoliang Shou , Weikang Yang , Sunao Takatori , Makoto Yamamoto
CPC分类号： G06J1/00
摘要： A multiplication circuit for multiplying analog values. The multiplication circuit receives a plurality of input voltages and selects one of the input voltages. The multiplication circuit also includes at least one resistor/capacitor (RC) circuit. The RC circuits includes a resistor for receiving a stepwise start signal and a capacitor, which is connected between a ground potential and the resistor. An output terminal is connected between the resistor and the capacitor. The output terminal outputs an output voltage. The multiplication circuit produces a stop signal when a difference between the selected one of the input voltages and the output voltage is greater than a predetermined value. The multiplication circuit selectively increases or decreases a count value by a number of clock pulses that occur between the stepwise start signal and the stop signal, The multiplication circuit produces a count signal, which is indicative of the count value. The multiplication circuit includes a switch for electrically disconnecting, in accordance with the count signal, the resistor and the capacitor of the RC circuit.
摘要翻译： 用于乘以模拟值的乘法电路。 乘法电路接收多个输入电压并选择输入电压之一。 乘法电路还包括至少一个电阻器/电容器（RC）电路。 RC电路包括用于接收逐步启动信号的电阻器和连接在接地电位和电阻器之间的电容器。 输出端连接在电阻和电容之间。 输出端输出输出电压。 当选择的输入电压和输出电压之间的差异大于预定值时，乘法电路产生停止信号。 乘法电路选择性地将计数值增加或减少在逐步启动信号和停止信号之间发生的时钟脉冲数。乘法电路产生计数信号，其表示计数值。 乘法电路包括根据计数信号电路断开RC电路的电阻器和电容器的开关。
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19.发明授权Digital filter circuit that minimizes holding errors transmitted between holding circuits 失效数字滤波电路使保持电路之间传输的保持误差最小化
公开(公告)号：US5396446A
公开(公告)日：1995-03-07
申请号：US155809
申请日：1993-11-23
申请人： Guoliang Shou , Weikang Yang , Sunao Takatori , Makoto Yamamoto
发明人： Guoliang Shou , Weikang Yang , Sunao Takatori , Makoto Yamamoto
CPC分类号： H03H17/0294 , G06J1/00 , H03H17/0225
摘要： A filter circuit that controls holding errors so that such errors are held to a minimum. In the filter circuit, multipliers of multiplication circuits are stored in a shift register and multiplication is successively executed with various multipliers in a multiplication circuit by circulating multipliers in the shift register.
摘要翻译： 控制保持误差使得将这些误差保持在最小的滤波器电路。 在滤波器电路中，乘法电路的乘法器存储在移位寄存器中，并且通过在移位寄存器中循环乘法器，在乘法电路中通过各种乘法器连续执行乘法运算。
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公开(公告)号：US5381352A
公开(公告)日：1995-01-10
申请号：US170731
申请日：1993-12-21
申请人： Guoliang Shou , Weikang Yang , Sunao Takatori , Makoto Yamamoto
发明人： Guoliang Shou , Weikang Yang , Sunao Takatori , Makoto Yamamoto
摘要： A multiplication circuit directly multiplying an analog and a digital data without converting analog/digital or digital/analog converting. An analog input voltage is controlled by a switching signal of a digital voltage so as to generate an analog output or cut-off the outputs. Digital input signals b.sub.0 to b.sub.7 of a plural number of bits is integrated giving weights by means of a capacitive coupling, and a sign bit is added by a capacitive coupling CP with a double weight of the most significant bit ("MSB") of the digital input.
摘要翻译： 乘法电路将模拟和数字数据直接相乘，而无需转换模拟/数字或数字/模拟转换。 模拟输入电压由数字电压的开关信号控制，以产生模拟输出或截止输出。 多个位的数字输入信号b0至b7被积分，通过电容耦合给出加权，并且通过电容耦合CP加上符号位，该电容耦合CP具有最高有效位（“MSB”）的双重权重 数字输入
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