公开(公告)号：US20170069639A1

公开(公告)日：2017-03-09

申请号：US15119989

申请日：2014-03-14

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Ning GE ,  Leong Yap CHIA ,  Jose Jehrome Rando

IPC: H01L27/115 ,  H01L29/788 ,  B41J2/14 ,  H01L29/423

CPC classification number: H01L27/11519 ,  B41J2/14 ,  H01L21/28273 ,  H01L27/11524 ,  H01L29/42324 ,  H01L29/4238 ,  H01L29/78 ,  H01L29/7881

Abstract: An electronically programmable read-only memory (EPROM) cell includes a semiconductor substrate having source and drain regions; a floating gate, adjacent to the source and drain regions and separated from the semiconductor substrate by a first dielectric layer, the floating gate including: a polysilicon layer formed over the first dielectric layer; a first metal layer electrically connected to the polysilicon layer, where the surface area of the first metal layer is less than 1000 μm2; and a control gate comprising a second metal layer, capacitively coupled to the first metal layer through a second dielectric material disposed therebetween.

Abstract translation: 电子可编程只读存储器（EPROM）单元包括具有源区和漏区的半导体衬底; 浮置栅极，与源极和漏极区相邻并且通过第一介电层与半导体衬底分离，所述浮置栅极包括：形成在第一介电层上的多晶硅层; 电连接到多晶硅层的第一金属层，其中第一金属层的表面积小于1000μm2; 以及包括第二金属层的控制栅极，所述第二金属层通过设置在其间的第二介电材料电容耦合到所述第一金属层。

公开(公告)号：US10403362B2

公开(公告)日：2019-09-03

申请号：US16255361

申请日：2019-01-23

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Boon Bing Ng ,  Thida Ma Win ,  Ning Ge ,  Jose Jehrome Rando

IPC: G11C16/06 ,  G11C16/14 ,  G11C8/12 ,  G11C16/08 ,  B41J2/175 ,  G11C19/28 ,  G11C19/00

Abstract: A split memory bank may comprise a number of memory matrices forming a memory bank and a shift register in which the shift register physically separates the matrices. An integrated circuit may comprise a number of shift registers and a plurality of memory matrices forming a memory bank in which the matrices are spatially separated by the shift register. An integrated printhead may comprise a number of memory banks each comprising a plurality of memory matrices and a number of shift registers in which each shift register spatially separates a number of the matrices.

公开(公告)号：US20190156892A1

公开(公告)日：2019-05-23

申请号：US16255361

申请日：2019-01-23

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Boon Bing Ng ,  Thida Ma Win ,  Ning Ge ,  Jose Jehrome Rando

IPC: G11C16/06 ,  G11C19/28 ,  B41J2/175 ,  G11C8/12 ,  G11C16/08

CPC classification number: G11C16/06 ,  B41J2/17546 ,  G11C8/12 ,  G11C16/08 ,  G11C19/00 ,  G11C19/28

Abstract: A split memory bank may comprise a number of memory matrices forming a memory bank and a shift register in which the shift register physically separates the matrices. An integrated circuit may comprise a number of shift registers and a plurality of memory matrices forming a memory bank in which the matrices are spatially separated by the shift register. An integrated printhead may comprise a number of memory banks each comprising a plurality of memory matrices and a number of shift registers in which each shift register spatially separates a number of the matrices.

公开(公告)号：US10236063B2

公开(公告)日：2019-03-19

申请号：US15986531

申请日：2018-05-22

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Boon Bing Ng ,  Thida Ma Win ,  Ning Ge ,  Jose Jehrome Rando

IPC: G11C16/06 ,  G11C8/12 ,  G11C16/08 ,  B41J2/175 ,  G11C19/28 ,  G11C16/14 ,  G11C19/00

Abstract: A split memory bank may comprise a number of memory matrices forming a memory bank and a shift register in which the shift register physically separates the matrices. An integrated circuit may comprise a number of shift registers and a plurality of memory matrices forming a memory bank in which the matrices are spatially separated by the shift register. An integrated printhead may comprise a number of memory banks each comprising a plurality of memory matrices and a number of shift registers in which each shift register spatially separates a number of the matrices.

公开(公告)号：US20180268905A1

公开(公告)日：2018-09-20

申请号：US15986531

申请日：2018-05-22

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Boon Bing Ng ,  Thida Ma Win ,  Ning Ge ,  Jose Jehrome Rando

IPC: G11C16/06 ,  B41J2/175 ,  G11C19/28

CPC classification number: G11C16/06 ,  B41J2/17546 ,  G11C8/12 ,  G11C16/08 ,  G11C19/00 ,  G11C19/28

Abstract: A split memory bank may comprise a number of memory matrices forming a memory bank and a shift register in which the shift register physically separates the matrices. An integrated circuit may comprise a number of shift registers and a plurality of memory matrices forming a memory bank in which the matrices are spatially separated by the shift register. An integrated printhead may comprise a number of memory banks each comprising a plurality of memory matrices and a number of shift registers in which each shift register spatially separates a number of the matrices.

公开(公告)号：US20170213596A1

公开(公告)日：2017-07-27

申请号：US15327927

申请日：2014-07-30

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Boon Bing Ng ,  Thida Ma Win ,  Ning Ge ,  Jose Jehrome Rando

IPC: G11C16/06 ,  B41J2/175 ,  G11C19/28

CPC classification number: G11C16/06 ,  B41J2/17546 ,  G11C8/12 ,  G11C16/08 ,  G11C19/00 ,  G11C19/28

Abstract: A split memory bank may comprise a number of memory matrices forming a memory bank and a shift register in which the shift register physically separates the matrices. An integrated circuit may comprise a number of shift registers and a plurality of memory matrices forming a memory bank in which the matrices are spatially separated by the shift register. An integrated printhead may comprise a number of memory banks each comprising a plurality of memory matrices and a number of shift registers in which each shift register spatially separates a number of the matrices.