公开(公告)号：US20170210124A1

公开(公告)日：2017-07-27

申请号：US15327774

申请日：2014-07-30

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Boon Bing Ng ,  Thida Ma Win ,  Ning Ge ,  Jose Jehrome Rando

IPC: B41J2/045

CPC classification number: B41J2/0455 ,  B41J2/04541 ,  B41J2/0458 ,  B41J2/04581

Abstract: A nozzle firing cell may comprise a firing transistor and a pre-charge transistor having a source and drain coupled between a pre-charge line and a gate of the firing transistor wherein the pre-charge line is routed over the gate of the pre-charge transistor. A fluid ejection device may comprise a circuit comprising a nozzle firing ceil, the nozzle firing cell comprising a firing transistor and a pre-charge transistor having a source and drain coupled between a pre-charge Sine and a gate of the firing transistor in which the pre-charge line is routed over the gate of the pre-charge transistor. A circuit may comprise a number of firing transistors and a number of pre-charge transistors each having a source and drain coupled between a pre-charge line and a gate of one of the firing transistors in which the pre-charge line is routed over each of the gates of the pre-charge transistors.

公开(公告)号：US10084062B2

公开(公告)日：2018-09-25

申请号：US15657401

申请日：2017-07-24

Applicant: Hewlett-Packard Development Company, L.P.

Inventor： Ning Ge ,  Leong Yap Chia ,  Pin Chin Lee ,  Jose Jehrome Rando

IPC: H01L29/66 ,  H01L21/332

CPC classification number: H01L29/66575 ,  H01L21/28035 ,  H01L21/28123 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/0847 ,  H01L29/66659 ,  H01L29/78 ,  H05K2203/013

Abstract: In some examples, a semiconductor device includes a substrate, a first doped region formed in the substrate, a second doped region around and spaced apart from the first doped region, and a channel between the first and second doped regions and formed using a gate ring on the substrate as a mask. A gate is formed over only a portion of the channel, the gate being a portion of the gate ring.

公开(公告)号：US10014055B2

公开(公告)日：2018-07-03

申请号：US15327927

申请日：2014-07-30

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Boon Bing Ng ,  Thida Ma Win ,  Ning Ge ,  Jose Jehrome Rando

IPC: G11C16/06 ,  B41J2/045 ,  G11C19/28 ,  B41J2/175

CPC classification number: G11C16/06 ,  B41J2/17546 ,  G11C8/12 ,  G11C16/08 ,  G11C19/00 ,  G11C19/28

Abstract: A split memory bank may comprise a number of memory matrices forming a memory bank and a shift register in which the shift register physically separates the matrices. An integrated circuit may comprise a number of shift registers and a plurality of memory matrices forming a memory bank in which the matrices are spatially separated by the shift register. An integrated printhead may comprise a number of memory banks each comprising a plurality of memory matrices and a number of shift registers in which each shift register spatially separates a number of the matrices.

公开(公告)号：US10384449B2

公开(公告)日：2019-08-20

申请号：US15910248

申请日：2018-03-02

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Boon Bing Ng ,  Thida Ma Win ,  Jose Jehrome Rando

IPC: B41J2/14 ,  H01L23/522 ,  H01L23/528 ,  H01L23/00

Abstract: In an example implementation, a grounding structure includes a perimeter ground line around the perimeter of a printhead die, and having north, south, east, and west segments. The structure includes an inter-slot ground line extending from the north segment to the south segment between two fluid slots, and an alternative ground line extending from the east segment to the west segment and intersecting the inter-slot ground line in a connection area near ends of the fluid slots.

公开(公告)号：US20180186151A1

公开(公告)日：2018-07-05

申请号：US15910248

申请日：2018-03-02

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Boon Bing Ng ,  Thida Ma Win ,  Jose Jehrome Rando

IPC: B41J2/14 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528

CPC classification number: B41J2/14072 ,  H01L23/5226 ,  H01L23/5286 ,  H01L24/06

Abstract: In an example implementation, a grounding structure includes a perimeter ground line around the perimeter of a printhead die, and having north, south, east, and west segments. The structure includes an inter-slot ground line extending from the north segment to the south segment between two fluid slots, and an alternative ground line extending from the east segment to the west segment and intersecting the inter-slot ground line in a connection area near ends of the fluid slots.

公开(公告)号：US09975335B2

公开(公告)日：2018-05-22

申请号：US15502588

申请日：2014-08-18

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Boon Bing Ng ,  Thida Ma Win ,  Jose Jehrome Rando

IPC: B41J2/14 ,  H01L23/528 ,  H01L23/522 ,  H01L23/00

CPC classification number: B41J2/14072 ,  H01L23/5226 ,  H01L23/5286 ,  H01L24/06

Abstract: In an example implementation, a grounding structure includes a perimeter ground line around the perimeter of a printhead die, and having north, south, east, and west segments. The structure includes an inter-slot ground line extending from the north segment to the south segment between two fluid slots, and an alternative ground line extending from the east segment to the west segment and intersecting the inter-slot ground line in a connection area near ends of the fluid slots.

公开(公告)号：US09953991B2

公开(公告)日：2018-04-24

申请号：US15119989

申请日：2014-03-14

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Ning Ge ,  Leong Yap Chia ,  Jose Jehrome Rando

IPC: H01L29/423 ,  H01L27/115 ,  H01L27/11519 ,  H01L29/78 ,  H01L29/788 ,  H01L27/11524 ,  H01L21/28 ,  B41J2/14

CPC classification number: H01L27/11519 ,  B41J2/14 ,  H01L21/28273 ,  H01L27/11524 ,  H01L29/42324 ,  H01L29/4238 ,  H01L29/78 ,  H01L29/7881

Abstract: An electronically programmable read-only memory (EPROM) cell includes a semiconductor substrate having source and drain regions; a floating gate, adjacent to the source and drain regions and separated from the semiconductor substrate by a first dielectric layer, the floating gate including: a polysilicon layer formed over the first dielectric layer; a first metal layer electrically connected to the polysilicon layer, where the surface area of the first metal layer is less than 1000 μm2; and a control gate comprising a second metal layer, capacitively coupled to the first metal layer through a second dielectric material disposed therebetween.

公开(公告)号：US10029457B2

公开(公告)日：2018-07-24

申请号：US15327774

申请日：2014-07-30

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Boon Bing Ng ,  Thida Ma Win ,  Ning Ge ,  Jose Jehrome Rando

IPC: B41J2/045

Abstract: A nozzle firing cell may comprise a firing transistor and a pre-charge transistor having a source and drain coupled between a pre-charge line and a gate of the firing transistor wherein the pre-charge line is routed over the gate of the pre-charge transistor. A fluid ejection device may comprise a circuit comprising a nozzle firing cell, the nozzle firing cell comprising a firing transistor and a pre-charge transistor having a source and drain coupled between a pre-charge Sine and a gate of the firing transistor in which the pre-charge line is routed over the gate of the pre-charge transistor. A circuit may comprise a number of firing transistors and a number of pre-charge transistors each having a source and drain coupled between a pre-charge line and a gate of one of the firing transistors in which the pre-charge line is routed over each of the gates of the pre-charge transistors.

公开(公告)号：US09786777B2

公开(公告)日：2017-10-10

申请号：US14913980

申请日：2013-08-30

Applicant: Hewlett-Packard Development Company, L.P.

Inventor： Ning Ge ,  Leong Yap Chia ,  Pin Chin Lee ,  Jose Jehrome Rando

IPC: H01L21/00 ,  H01L29/74 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28 ,  H01L29/08 ,  H01L21/8234

CPC classification number: H01L29/66575 ,  H01L21/28035 ,  H01L21/28123 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/0847 ,  H01L29/66659 ,  H01L29/78 ,  H05K2203/013

Abstract: A semiconductor device and method of forming the same is described. In an example, a polysilicon layer is deposited on a substrate having at least one polysilicon ring. The substrate is doped using the polysilicon layer as a mask to form doped regions in the substrate. A dielectric layer is deposited over the polysilicon layer and the substrate. The dielectric layer is etched to expose portions of the polysilicon layer. A metal layer is deposited on the dielectric layer. The metal layer, the dielectric layer, and the exposed portions of the polysilicon layer are etched such that at least a portion of each polysilicon ring is removed.

公开(公告)号：US20170225462A1

公开(公告)日：2017-08-10

申请号：US15502588

申请日：2014-08-18

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Boon Bing Ng ,  Thida Ma Win ,  Jose Jehrome Rando

IPC: B41J2/14 ,  H01L23/522 ,  H01L23/00 ,  H01L23/528

CPC classification number: B41J2/14072 ,  H01L23/5226 ,  H01L23/5286 ,  H01L24/06

Abstract: In an example implementation, a grounding structure includes a perimeter ground line around the perimeter of a printhead die, and having north, south, east, and west segments. The structure includes an inter-slot ground line extending from the north segment to the south segment between two fluid slots, and an alternative ground line extending from the east segment to the west segment and intersecting the inter-slot ground line in a connection area near ends of the fluid slots.