公开(公告)号：US20150221351A1

公开(公告)日：2015-08-06

申请号：US14567652

申请日：2014-12-11

申请人： SANG-WON PARK ,  KITAE PARK ,  SANG-WON SHIM

发明人： SANG-WON PARK ,  KITAE PARK ,  SANG-WON SHIM

IPC分类号： G11C7/12 ,  G11C7/04 ,  G11C7/10 ,  G11C5/02

CPC分类号： G11C8/08 ,  G11C5/02 ,  G11C7/04 ,  G11C8/10 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/30 ,  G11C16/32

摘要： A word line driving method is for a nonvolatile memory device including a plurality of memory blocks having a plurality of strings which is formed in a direction perpendicular to a substrate and connected between bit lines and a common source line. The method includes applying an offset pulse to a word line for a predetermined time to shorten a word line setting time, and applying a target pulse having a level which is higher or lower than a level of the offset pulse to the word line after the predetermined time.

摘要翻译： 字线驱动方法是用于非易失性存储器件，其包括具有多个串的多个存储块，所述多个存储块形成在与衬底垂直的方向上并连接在位线和公共源极线之间。 该方法包括将偏移脉冲施加到字线预定时间以缩短字线设置时间，并且在预定的时间之后将具有高于或低于偏移脉冲的电平的电平的目标脉冲施加到字线 时间。

公开(公告)号：US20150049545A1

公开(公告)日：2015-02-19

申请号：US14278743

申请日：2014-05-15

申请人： JONGHOO JO ,  HYUN JUN YOON ,  KITAE PARK ,  DONGKYO SHIM

发明人： JONGHOO JO ,  HYUN JUN YOON ,  KITAE PARK ,  DONGKYO SHIM

IPC分类号： G11C16/34 ,  G11C16/10

CPC分类号： G11C16/3459 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10

摘要： A method of programming a nonvolatile memory device comprises performing an N-th program loop based on state data stored in data latches according to a default state ordering, determining whether conversion of the default state ordering is required according to a predetermined criterion, as a consequence of determining that conversion of the default state ordering is required, converting all or part of the state data stored in the data latches from the default state ordering to another state ordering, and performing a (N+1)th program loop based on the converted state data.

摘要翻译： 一种非易失性存储器件的编程方法包括：根据默认状态顺序，根据存储在数据锁存器中的状态数据执行第N个程序循环，确定是否需要根据预定标准转换默认状态排序，结果 确定需要转换默认状态排序，将存储在数据锁存器中的全部或部分状态数据从默认状态排序转换到另一状态排序，以及基于转换的第（N + 1）个程序循环执行 状态数据。

公开(公告)号：US20120314500A1

公开(公告)日：2012-12-13

申请号：US13477161

申请日：2012-05-22

申请人： YOUNGSUN SONG ,  BOGEUN KIM ,  OHSUK KWON ,  KITAE PARK ,  SEUNG-HWAN SHIN ,  SANGYONG YOON

发明人： YOUNGSUN SONG ,  BOGEUN KIM ,  OHSUK KWON ,  KITAE PARK ,  SEUNG-HWAN SHIN ,  SANGYONG YOON

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C16/10 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/08 ,  G11C16/34 ,  G11C16/3459

摘要： A nonvolatile memory device includes a memory cell array, a page buffer unit which output a verify-read result, a reference current generating unit which generates a reference current signal, a page buffer decoding unit which outputs currents according to the verify-read result. The nonvolatile memory device further includes an analog bit counting unit which counts the currents, a digital adding unit which calculates an accumulated sum of the counting result, a pass/fail checking unit which outputs a pass signal or fail signal according to the calculation result, and a control unit controlling a program operation.

摘要翻译： 非易失性存储器件包括存储单元阵列，输出验证读取结果的页面缓冲器单元，产生参考电流信号的参考电流产生单元，根据验证读取结果输出电流的页面缓冲器解码单元。 非易失性存储装置还包括对电流进行计数的模拟比特计数单元，计算计数结果的累计和的数字加法单元，根据计算结果输出通过信号或失败信号的通过/失败检查单元， 以及控制程序操作的控制单元。

公开(公告)号：US20160071592A1

公开(公告)日：2016-03-10

申请号：US14945354

申请日：2015-11-18

申请人： SANG-WAN NAM ,  KITAE PARK

发明人： SANG-WAN NAM ,  KITAE PARK

IPC分类号： G11C16/04 ,  G11C16/08 ,  G11C16/10

CPC分类号： G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/3427

摘要： A three-dimensional (3D) flash memory includes a first dummy word line disposed between a ground select line and a lowermost main word line, and a second dummy word line of different word line configuration disposed between a string select line and an upper most main word line.

公开(公告)号：US20140347927A1

公开(公告)日：2014-11-27

申请号：US14244930

申请日：2014-04-04

申请人： MINSU KIM ,  YANG-LO AHN ,  DAE HAN KIM ,  KITAE PARK

发明人： MINSU KIM ,  YANG-LO AHN ,  DAE HAN KIM ,  KITAE PARK

IPC分类号： G11C16/08

CPC分类号： G11C16/08 ,  G11C16/0483 ,  G11C16/3427

摘要： A nonvolatile memory device comprises a plurality of vertical NAND flash memory cells arranged in a three dimensional (3D) structure, a first memory block disposed in the 3D structure and having memory cells selected by a first ground selection line and a second ground selection line, wherein the first and second ground selection lines are electrically separated from each other, a second memory block disposed in the 3D structure and having memory cells selected by a third selection line and fourth selection line, wherein the third and fourth ground selection lines are electrically separated from each other, and a pass transistor that transfers a driving signal to turn on ground selection transistors respectively connected to the first and third ground selection lines in response to a block selection signal.

摘要翻译： 非易失性存储器件包括以三维（3D）结构排列的多个垂直NAND闪存单元，设置在3D结构中的第一存储器块，并具有由第一接地选择线和第二接地选择线选择的存储单元， 其中所述第一和第二接地选择线彼此电分离，设置在所述3D结构中并具有由第三选择线和第四选择线选择的存储单元的第二存储器块，其中所述第三和第四接地选择线被电分离 以及传递驱动信号以通过响应于块选择信号接通分别连接到第一和第三接地选择线的接地选择晶体管的传输晶体管。

公开(公告)号：US20140226403A1

公开(公告)日：2014-08-14

申请号：US14056268

申请日：2013-10-17

申请人： SANG-WAN NAM ,  MINSU KIM ,  KANG-BIN LEE ,  KITAE PARK

发明人： SANG-WAN NAM ,  MINSU KIM ,  KANG-BIN LEE ,  KITAE PARK

IPC分类号： G11C16/08

CPC分类号： G11C16/24 ,  G11C5/147 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3418 ,  G11C16/3459

摘要： A method is provided for driving a nonvolatile memory device, including multiple strings, where each string is formed by penetrating plate-shaped word lines stacked on a substrate. The method includes configuring the word lines of a string in multiple zones based on zone configuration information, and applying zone voltages to the zones, respectively. The zone configuration information is varied according to a mode of operation.

摘要翻译： 提供一种用于驱动包括多个串的非易失性存储器件的方法，其中通过穿过堆叠在衬底上的板状字线形成每个串。 该方法包括基于区域配置信息配置多个区域中的字符串的字线，并且将区域电压分别应用于区域。 区域配置信息根据操作模式而变化。