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    Concurrent Execution of Critical Sections by Eliding Ownership of Locks
    12.
    发明申请
    Concurrent Execution of Critical Sections by Eliding Ownership of Locks 审中-公开
    通过确定锁定所有权并行执行关键部分

    公开(公告)号：US20110225375A1

    公开(公告)日：2011-09-15

    申请号：US13113432

    申请日：2011-05-23

    申请人： Ravi Rajwar ,  James R. Goodman

    发明人： Ravi Rajwar ,  James R. Goodman

    IPC分类号： G06F12/00

    CPC分类号： G06F9/528 ,  G06F9/3004 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/52 ,  G06F12/0808 ,  G06F12/0844 ,  G06F12/0891 ,  G06F12/12 ,  G06F12/128 ,  G06F12/1458 ,  G06F12/1475 ,  G06F2212/1041 ,  G06F2212/1052 ,  G06F2212/283 ,  G06F2212/62

    摘要： One embodiment of the present invention provides a system that facilitates avoiding locks by speculatively executing critical sections of code. During operation, the system allows a process to speculatively execute a critical section of code within a program without first acquiring a lock associated with the critical section. If the process subsequently completes the critical section without encountering an interfering data access from another process, the system commits changes made during the speculative execution, and resumes normal non-speculative execution of the program past the critical section. Otherwise, if an interfering data access from another process is encountered during execution of the critical section, the system discards changes made during the speculative execution, and attempts to re-execute the critical section.

    摘要翻译： 本发明的一个实施例提供一种通过推测性地执行代码的关键部分来有助于避免锁定的系统。 在操作期间，系统允许进程在程序中推测性地执行代码的关键部分而不首先获得与关键部分相关联的锁定。 如果该过程随后完成关键部分而没有遇到来自另一进程的干扰数据访问，则系统进行在推测执行期间所做的更改，并且通过关键部分恢复程序的正常非推测性执行。 否则，如果在执行关键部分期间遇到来自其他进程的干扰数据访问，则系统将丢弃在推测执行期间所做的更改，并尝试重新执行临界部分。

    Concurrent execution of critical sections by eliding ownership of locks
    14.
    发明授权
    Concurrent execution of critical sections by eliding ownership of locks 有权
    通过查看锁的所有权并发执行关键部分

    公开(公告)号：US07962699B2

    公开(公告)日：2011-06-14

    申请号：US12843828

    申请日：2010-07-26

    申请人： Ravi Rajwar ,  James R. Goodman

    发明人： Ravi Rajwar ,  James R. Goodman

    IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28

    CPC分类号： G06F9/528 ,  G06F9/3004 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/52 ,  G06F12/0808 ,  G06F12/0844 ,  G06F12/0891 ,  G06F12/12 ,  G06F12/128 ,  G06F12/1458 ,  G06F12/1475 ,  G06F2212/1041 ,  G06F2212/1052 ,  G06F2212/283 ,  G06F2212/62 ,  G06F2212/69

    摘要： One embodiment of the present invention provides a system that facilitates avoiding locks by speculatively executing critical sections of code. During operation, the system allows a process to speculatively execute a critical section of code within a program without first acquiring a lock associated with the critical section. If the process subsequently completes the critical section without encountering an interfering data access from another process, the system commits changes made during the speculative execution, and resumes normal non-speculative execution of the program past the critical section. Otherwise, if an interfering data access from another process is encountered during execution of the critical section, the system discards changes made during the speculative execution, and attempts to re-execute the critical section.

    摘要翻译： 本发明的一个实施例提供一种通过推测性地执行代码的关键部分来有助于避免锁定的系统。 在操作期间，系统允许进程在程序中推测性地执行代码的关键部分而不首先获得与关键部分相关联的锁定。 如果该过程随后完成关键部分而没有遇到来自另一进程的干扰数据访问，则系统进行在推测执行期间所做的更改，并且通过关键部分恢复程序的正常非推测性执行。 否则，如果在执行关键部分期间遇到来自其他进程的干扰数据访问，则系统将丢弃在推测执行期间所做的更改，并尝试重新执行临界部分。

    Critical section detection and prediction mechanism for hardware lock elision
    15.
    发明申请
    Critical section detection and prediction mechanism for hardware lock elision 有权
    硬件锁定检测的关键部分检测和预测机制

    公开(公告)号：US20080115042A1

    公开(公告)日：2008-05-15

    申请号：US11599009

    申请日：2006-11-13

    申请人： Haitham Akkary ,  Ravi Rajwar ,  Srikanth T. Srinivasan

    发明人： Haitham Akkary ,  Ravi Rajwar ,  Srikanth T. Srinivasan

    IPC分类号： H03M13/51

    CPC分类号： G06F9/3865 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/528

    摘要： A method and apparatus for detecting lock instructions and lock release instruction, as well as predicting critical sections is herein described. A lock instruction is detected with detection logic, which potentially resides in decode logic. A lock instruction entry associated with the lock instruction is stored/created. Address locations and values to be written to those address location of subsequent potential lock release instruction are compared to the address loaded from by the lock instruction and the value load by the lock instruction. If the addresses and values match, it is determined that the lock release instruction matches the lock instruction. A prediction entry stores a reference to the lock instruction, such as a last instruction pointer (LIP), and an associated value to represent the lock instruction is to be elided upon subsequent detection, if it is determined that the lock release instruction matches the lock instruction.

    摘要翻译： 这里描述了用于检测锁定指令和锁定释放指令以及预测关键部分的方法和装置。 检测逻辑检测到锁定指令，这可能存在于解码逻辑中。 存储/创建与锁定指令相关联的锁定指令条目。 将要写入后续潜在锁定释放指令的地址位置的地址位置和值与通过锁定指令加载的地址和锁定指令的值负载进行比较。 如果地址和值匹配，则确定锁定释放指令与锁定指令匹配。 预测条目存储对诸如最后指令指针（LIP）的锁定指令的引用，并且如果确定锁定解除指令与锁定相匹配，则在后续检测时将要消除表示锁定指令的关联值 指令。

    Per-set relaxation of cache inclusion
    16.
    发明申请
    Per-set relaxation of cache inclusion 审中-公开
    缓存包容的放松

    公开(公告)号：US20070143550A1

    公开(公告)日：2007-06-21

    申请号：US11313114

    申请日：2005-12-19

    申请人： Ravi Rajwar ,  Matthew Mattina

    发明人： Ravi Rajwar ,  Matthew Mattina

    IPC分类号： G06F13/28

    CPC分类号： G06F12/0811 ,  G06F12/084

    摘要： A multi-core processor includes a plurality of processors and a shared cache. Cache control logic implements an inclusive cache scheme among the shared cache and the local caches for the processors. Counters are maintained to track instances, per set, when a processor chooses to delay eviction from the local cache. While the counter indicates that one or more delayed evictions are pending for a set, the cache control logic treats the set as non-inclusive, broadcasting foreign snoops to all of the local caches, regardless of whether the snoop hits in the shared cache. Other embodiments are also described and claimed.

    摘要翻译： 多核处理器包括多个处理器和共享高速缓存。 缓存控制逻辑在共享高速缓存和处理器的本地高速缓存之间实现包容性高速缓存方案。 当处理器选择延迟从本地缓存驱逐时，计数器被维护以跟踪每集的实例。 虽然计数器指示一个或多个延迟的撤离正在等待一组，但是高速缓存控制逻辑将该集合视为非包容性，将广播外部侦听广播到所有本地高速缓存，而不管窥探者是否在共享高速缓存中命中。 还描述和要求保护其他实施例。

    Runahead execution in a central processing unit
    17.
    发明申请
    Runahead execution in a central processing unit 审中-公开
    Runahead执行在中央处理单元

    公开(公告)号：US20060149931A1

    公开(公告)日：2006-07-06

    申请号：US11024164

    申请日：2004-12-28

    申请人： Akkary Haitham ,  Doron Orenstein ,  Ravi Rajwar ,  Srikanth Srinivasan

    发明人： Akkary Haitham ,  Doron Orenstein ,  Ravi Rajwar ,  Srikanth Srinivasan

    IPC分类号： G06F9/30

    CPC分类号： G06F9/3824 ,  G06F9/3842

    摘要： According to one embodiment, a method is disclosed. The method includes detecting a load miss at a central processing unit (CPU), stalling a read only buffer (ROB), speculatively retiring an instruction causing the ROB stall and subsequent instructions, keeping registers that have not been renamed in the ROB upon retirement, and flushing the CPU pipeline upon receiving data from the load miss.

    摘要翻译： 根据一个实施例，公开了一种方法。 该方法包括检测在中央处理单元（CPU）处的负载未命中，阻止只读缓冲器（ROB），推测性地退出导致ROB停顿的指令和后续指令，在退出时保持尚未重命名在ROB中的寄存器， 并在接收到载入错误的数据时刷新CPU管道。

    Back-end renaming in a continual flow processor pipeline
    18.
    发明申请
    Back-end renaming in a continual flow processor pipeline 有权

    公开(公告)号：US20060095738A1

    公开(公告)日：2006-05-04

    申请号：US10953761

    申请日：2004-09-30

    申请人： Haitham Akkary ,  Ravi Rajwar ,  Srinivasan Srikanth

    发明人： Haitham Akkary ,  Ravi Rajwar ,  Srinivasan Srikanth

    IPC分类号： G06F9/30

    CPC分类号： G06F9/3842 ,  G06F9/384

    摘要： Embodiments of the present invention relate to a system and method for comparatively increasing processor throughput and relieving pressure on the processor's scheduler and register file by diverting instructions dependent on long-latency operations from a flow of the processor pipeline and re-introducing the instructions into the flow when the long-latency operations are completed. In this way, the instructions do not tie up resources and overall instruction throughput in the pipeline is comparatively increased. Before the instructions are diverted from the pipeline, they may undergo a conventional process to map logical registers of the instructions to physical registers. Before the instructions are re-introduced into the pipeline, the physical registers mapped according to the conventional process may be re-mapped to other physical registers, thereby efficiently preserving correct program sequence information.