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17 条记录 (耗时 0.026 秒)

    Method of producing a thin semiconductor chip
    13.
    发明授权
    Method of producing a thin semiconductor chip 有权
    薄半导体芯片的制造方法

    公开(公告)号：US07863104B2

    公开(公告)日：2011-01-04

    申请号：US12246983

    申请日：2008-10-07

    申请人： Werner Kroeninger ,  Manfred Kotek ,  Adolf Koller ,  Abdul Rahman Mohamed

    发明人： Werner Kroeninger ,  Manfred Kotek ,  Adolf Koller ,  Abdul Rahman Mohamed

    IPC分类号： H01L21/00

    CPC分类号： H01L21/78 ,  H01L21/6835 ,  H01L2221/68318 ,  H01L2221/68331

    摘要： A method of fabricating a semiconductor chip includes the providing an adhesive layer on the outer area of the active surface of a device wafer and attaching a rigid body to the active surface by the adhesive layer. The device wafer is thinned by treating the passive surface of the device wafer. A first backing tape is connected to the passive surface of the device wafer. The outer portion of the rigid body is separated from the central portion of the rigid body and the outer portion of the device wafer is separated from the central portion of the device wafer. The central portion of the rigid body, the outer portion of the device wafer and the outer portion of the rigid body are removed from the first backing tape. The device wafer may be diced into semiconductor chips.

    摘要翻译： 制造半导体芯片的方法包括在器件晶片的有源表面的外部区域上提供粘合剂层，并通过粘合剂层将刚性体附着到活性表面。 通过处理器件晶片的被动表面来使器件晶片变薄。 第一背衬带连接到器件晶片的被动表面。 刚体的外部与刚体的中心部分分离，并且装置晶片的外部与装置晶片的中心部分分开。 刚性体的中心部分，装置晶片的外部部分和刚体的外部部分从第一背衬带上移除。 器件晶片可以切成半导体芯片。

    Power transistor arrangement and method for fabricating it
    15.
    发明授权
    Power transistor arrangement and method for fabricating it 有权
    功率晶体管布置及其制造方法

    公开(公告)号：US07186618B2

    公开(公告)日：2007-03-06

    申请号：US10977118

    申请日：2004-10-29

    申请人： Martin Pölzl ,  Franz Hirler ,  Oliver Häberlen ,  Manfred Kotek ,  Walter Rieger

    发明人： Martin Pölzl ,  Franz Hirler ,  Oliver Häberlen ,  Manfred Kotek ,  Walter Rieger

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7813 ,  H01L29/402 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/4238 ,  H01L29/7811

    摘要： When fabricating trench power transistor arrangements (1) with active cell array trenches (5) and passive connecting trenches (6), the cell array trenches (5) are provided in greater width than the connecting trenches (6). An auxiliary layer (24) is deposited conformally onto a lower field electrode structure (11) in the cell array trenches (5) and the connecting trenches (6) and is etched back as far as the top edge in the connecting trenches (6), which removes it from the cell array trenches (5). The auxiliary layer (24) allows the gate oxide (20) to be patterned without a complex mask process. An edge trench (7), with an electrode, on the potential of the field electrode structure (11) shields the cell array (3) from a drain potential.

    摘要翻译： 当制造具有有源电池阵列沟槽（5）和无源连接沟槽（6）的沟槽功率晶体管布置（1）时，电池阵列沟槽（5）的宽度大于连接沟槽（6）。 辅助层（24）保形地沉积在单元阵列沟槽（5）和连接沟槽（6）中的下部电场结构（11）上并被回蚀到连接沟槽（6）中的顶部边缘， ，其从单元阵列沟槽（5）中移除它。 辅助层（24）允许栅极氧化物（20）被图案化而不需要复杂的掩模工艺。 在场电极结构（11）的电位上具有电极的边缘沟槽（7）将电池阵列（3）与漏极电势屏蔽。

    Power transistor arrangement and method for fabricating it
    16.
    发明申请
    Power transistor arrangement and method for fabricating it 有权
    功率晶体管布置及其制造方法

    公开(公告)号：US20050145936A1

    公开(公告)日：2005-07-07

    申请号：US10977118

    申请日：2004-10-29

    申请人： Martin Polzl ,  Franz Hirler ,  Oliver Haberlen ,  Manfred Kotek ,  Walter Rieger

    发明人： Martin Polzl ,  Franz Hirler ,  Oliver Haberlen ,  Manfred Kotek ,  Walter Rieger

    IPC分类号： H01L21/336 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78

    CPC分类号： H01L29/7813 ,  H01L29/402 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/4238 ,  H01L29/7811

    摘要： When fabricating trench power transistor arrangements (1) with active cell array trenches (5) and passive connecting trenches (6), the cell array trenches (5) are provided in greater width than the connecting trenches (6). An auxiliary layer (24) is deposited conformally onto a lower field electrode structure (11) in the cell array trenches (5) and the connecting trenches (6) and is etched back as far as the top edge in the connecting trenches (6), which removes it from the cell array trenches (5). The auxiliary layer (24) allows the gate oxide (20) to be patterned without a complex mask process. An edge trench (7), with an electrode, on the potential of the field electrode structure (11) shields the cell array (3) from a drain potential.

    摘要翻译： 当制造具有有源电池阵列沟槽（5）和无源连接沟槽（6）的沟槽功率晶体管布置（1）时，电池阵列沟槽（5）的宽度大于连接沟槽（6）。 辅助层（24）保形地沉积在单元阵列沟槽（5）和连接沟槽（6）中的下部电场结构（11）上并被回蚀到连接沟槽（6）中的顶部边缘， ，其从单元阵列沟槽（5）中移除它。 辅助层（24）允许栅极氧化物（20）被图案化而不需要复杂的掩模工艺。 在场电极结构（11）的电位上具有电极的边缘沟槽（7）将电池阵列（3）与漏极电势屏蔽。