公开(公告)号：US08409949B2

公开(公告)日：2013-04-02

申请号：US12822157

申请日：2010-06-23

申请人： Tsuyoshi Arigane ,  Digh Hisamoto ,  Yasuhiro Shimamoto ,  Toshiyuki Mine

发明人： Tsuyoshi Arigane ,  Digh Hisamoto ,  Yasuhiro Shimamoto ,  Toshiyuki Mine

IPC分类号： H01L21/336

CPC分类号： H01L29/42328 ,  G11C16/3418 ,  H01L27/11521 ,  H01L27/1203 ,  H01L29/7883

摘要： Provided is a nonvolatile semiconductor memory device highly integrated and highly reliable. A plurality of memory cells are formed in a plurality of active regions sectioned by a plurality of isolations (silicon oxide films) extending in the Y direction and deeper than a well (p type semiconductor region). In each memory cell, a contact is provided in the well (p type semiconductor region) so as to penetrate through a source diffusion layer (n+ type semiconductor region), and the contact that electrically connects bit lines (metal wirings) and the source diffusion layer (n+ type semiconductor region) is also electrically connected to the well (p type semiconductor region).

摘要翻译： 提供了高度集成且高度可靠的非易失性半导体存储器件。 多个存储单元形成在由在Y方向上延伸并且比阱（p型半导体区域）更深的多个隔离（氧化硅膜）分割的多个有源区域中。 在每个存储单元中，在阱（p型半导体区域）中提供接触以穿透源极扩散层（n +型半导体区域），并且将位线（金属布线）和源极扩散 层（n +型半导体区）也与阱（p型半导体区）电连接。

公开(公告)号：US08044455B2

公开(公告)日：2011-10-25

申请号：US12683935

申请日：2010-01-07

申请人： Yutaka Okuyama ,  Tsuyoshi Arigane

发明人： Yutaka Okuyama ,  Tsuyoshi Arigane

IPC分类号： H01L29/792

CPC分类号： H01L21/28282 ,  H01L27/11529 ,  H01L27/11565 ,  H01L27/11568

摘要： A step is provided between a substrate surface of a select gate and a substrate surface of a memory gate. When the substrate surface of the select gate is lower than the substrate surface of the memory gate, electrons in a channel upon writing obliquely flow in the step portion. Even if the electrons obtain the energy required for passing a barrier during the oblique flow, the electron injection does not occur because electrons are away from the substrate surface. The injection can occur only on a drain region side from a position where the electrons reach the substrate surface. As a result, the injection of the electrons into a gap region is suppressed, so that the electron distribution comes close to the hole distribution. Therefore, variation in a threshold value upon information retention is suppressed, and information-retaining characteristics of a memory cell are improved.

摘要翻译： 在选择栅极的衬底表面和存储栅极的衬底表面之间提供一个步骤。 当选择栅极的衬底表面低于存储栅极的衬底表面时，写入中的通道中的电子在阶跃部分中倾斜地流动。 即使电子获得在斜流期间通过势垒所需的能量，电子注入也不会发生，因为电子远离衬底表面。 注入只能在电子到达基板表面的位置的漏极区域侧发生。 结果，电子注入到间隙区域被抑制，使得电子分布接近孔分布。 因此，抑制信息保持时的阈值的变化，提高存储单元的信息保持特性。

公开(公告)号：US20100193856A1

公开(公告)日：2010-08-05

申请号：US12683935

申请日：2010-01-07

申请人： Yutaka Okuyama ,  Tsuyoshi Arigane

发明人： Yutaka Okuyama ,  Tsuyoshi Arigane

IPC分类号： H01L27/115 ,  H01L21/8246

CPC分类号： H01L21/28282 ,  H01L27/11529 ,  H01L27/11565 ,  H01L27/11568

摘要： A step is provided between a substrate surface of a select gate and a substrate surface of a memory gate. When the substrate surface of the select gate is lower than the substrate surface of the memory gate, electrons in a channel upon writing obliquely flow in the step portion. Even if the electrons obtain the energy required for passing a barrier during the oblique flow, the electron injection does not occur because electrons are away from the substrate surface. The injection can occur only on a drain region side from a position where the electrons reach the substrate surface. As a result, the injection of the electrons into a gap region is suppressed, so that the electron distribution comes close to the hole distribution. Therefore, variation in a threshold value upon information retention is suppressed, and information-retaining characteristics of a memory cell are improved.

摘要翻译： 在选择栅极的衬底表面和存储栅极的衬底表面之间提供一个步骤。 当选择栅极的衬底表面低于存储栅极的衬底表面时，写入中的通道中的电子在阶跃部分中倾斜地流动。 即使电子获得在斜流期间通过势垒所需的能量，电子注入也不会发生，因为电子远离衬底表面。 注入只能在电子到达基板表面的位置的漏极区域侧发生。 结果，电子注入到间隙区域被抑制，使得电子分布接近孔分布。 因此，抑制信息保持时的阈值的变化，提高存储单元的信息保持特性。

公开(公告)号：US08796756B2

公开(公告)日：2014-08-05

申请号：US13755348

申请日：2013-01-31

申请人： Kenichi Akita ,  Daisuke Okada ,  Keisuke Kuwahara ,  Yasafumi Morimoto ,  Yasuhiro Shimamoto ,  Kan Yasui ,  Tsuyoshi Arigane ,  Tetsuya Ishimaru

发明人： Kenichi Akita ,  Daisuke Okada ,  Keisuke Kuwahara ,  Yasafumi Morimoto ,  Yasuhiro Shimamoto ,  Kan Yasui ,  Tsuyoshi Arigane ,  Tetsuya Ishimaru

IPC分类号： H01L29/792

CPC分类号： H01L29/66833 ,  H01L27/115 ,  H01L27/11563 ,  H01L27/11568 ,  H01L29/792

摘要： A charge storage layer interposed between a memory gate electrode and a semiconductor substrate is formed shorter than a gate length of the memory gate electrode or a length of insulating films so as to make the overlapping amount of the charge storage layer and a source region to be less than 40 nm. Therefore, in the write state, since the movement in the transverse direction of the electrons and the holes locally existing in the charge storage layer decreases, the variation of the threshold voltage when holding a high temperature can be reduced. In addition, the effective channel length is made to be 30 nm or less so as to reduce an apparent amount of holes so that coupling of the electrons with the holes in the charge storage layer decreases; therefore, the variation of the threshold voltage when holding at room temperature can be reduced.

摘要翻译： 插入在存储栅电极和半导体衬底之间的电荷存储层形成为比存储栅电极的栅极长度或绝缘膜的长度短，以使电荷存储层和源极区域的重叠量成为 小于40nm。 因此，在写入状态下，由于在电荷存储层中局部存在的电子和空穴的横向的移动减少，因此可以降低保持高温时的阈值电压的变化。 此外，有效沟道长度为30nm以下，以减少空穴的表观量，使得电子与电荷存储层中的空穴的耦合减小; 因此，可以降低在室温下保持时的阈值电压的变化。

公开(公告)号：US08385124B2

公开(公告)日：2013-02-26

申请号：US13075169

申请日：2011-03-29

申请人： Tsuyoshi Arigane ,  Digh Hisamoto ,  Yasuhiro Shimamoto ,  Yutaka Okuyama

发明人： Tsuyoshi Arigane ,  Digh Hisamoto ,  Yasuhiro Shimamoto ,  Yutaka Okuyama

IPC分类号： G11C16/04

CPC分类号： H01L21/28282 ,  G11C16/0466 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/78 ,  H01L29/792

摘要： The semiconductor device includes the nonvolatile memory cell in the main surface of a semiconductor substrate. The nonvolatile memory cell has a first insulating film over the semiconductor substrate, a conductive film, a second insulating film, the charge storage film capable of storing therein charges, a third insulating film over the charge storage film, a first gate electrode, a fourth insulating film in contact with the set of stacked films from the first insulating film to the foregoing first gate electrode, a fifth insulating film juxtaposed with the first insulating film over the foregoing semiconductor substrate, a second gate electrode formed over the fifth insulating film to be adjacent to the foregoing first gate electrode over the side surface of the fourth insulating film, and source/drain regions with the first and second gate electrodes interposed therebetween. The conductive film and the charge storage film are formed to two-dimensionally overlap.

摘要翻译： 半导体器件包括在半导体衬底的主表面中的非易失性存储单元。 非易失性存储单元在半导体衬底上具有第一绝缘膜，导电膜，第二绝缘膜，能够存储电荷的电荷存储膜，电荷存储膜上的第三绝缘膜，第一栅电极，第四绝缘膜 绝缘膜与从第一绝缘膜到前述第一栅电极的层叠膜接触;第五绝缘膜，与上述半导体衬底上的第一绝缘膜并置，形成在第五绝缘膜上的第二栅电极， 与第四绝缘膜的侧表面上的上述第一栅电极相邻，以及其间插入第一和第二栅电极的源/漏区。 导电膜和电荷存储膜形成为二维重叠。

公开(公告)号：US20090134449A1

公开(公告)日：2009-05-28

申请号：US12273308

申请日：2008-11-18

申请人： Tsuyoshi Arigane ,  Digh Hisamoto ,  Yasuhiro Shimamoto ,  Toshiyuki Mine

发明人： Tsuyoshi Arigane ,  Digh Hisamoto ,  Yasuhiro Shimamoto ,  Toshiyuki Mine

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L29/42328 ,  G11C16/3418 ,  H01L27/11521 ,  H01L27/1203 ,  H01L29/7883

摘要： Provided is a nonvolatile semiconductor memory device highly integrated and highly reliable. A plurality of memory cells are formed in a plurality of active regions sectioned by a plurality of isolations (silicon oxide films) extending in the Y direction and deeper than a well (p type semiconductor region). In each memory cell, a contact is provided in the well (p type semiconductor region) so as to penetrate through a source diffusion layer (n+ type semiconductor region), and the contact that electrically connects bit lines (metal wirings) and the source diffusion layer (n+ type semiconductor region) is also electrically connected to the well (p type semiconductor region).

摘要翻译： 提供了高度集成且高度可靠的非易失性半导体存储器件。 多个存储单元形成在由在Y方向上延伸并且比阱（p型半导体区域）更深的多个隔离（氧化硅膜）分割的多个有源区域中。 在每个存储单元中，在阱（p型半导体区域）中提供接触以穿透源极扩散层（n +型半导体区域），并且将位线（金属布线）和源极扩散 层（n +型半导体区）也与阱（p型半导体区）电连接。

公开(公告)号：US20130140622A1

公开(公告)日：2013-06-06

申请号：US13755348

申请日：2013-01-31

申请人： Kenichi Akita ,  Daisuke Okada ,  Keisuke Kuwahara ,  Yasufumi Morimoto ,  Yasuhiro Shimamoto ,  Kan Yasui ,  Tsuyoshi Arigane ,  Tetsuya Ishimaru

发明人： Kenichi Akita ,  Daisuke Okada ,  Keisuke Kuwahara ,  Yasufumi Morimoto ,  Yasuhiro Shimamoto ,  Kan Yasui ,  Tsuyoshi Arigane ,  Tetsuya Ishimaru

IPC分类号： H01L29/792 ,  H01L29/66

CPC分类号： H01L29/66833 ,  H01L27/115 ,  H01L27/11563 ,  H01L27/11568 ,  H01L29/792

摘要： A charge storage layer interposed between a memory gate electrode and a semiconductor substrate is formed shorter than a gate length of the memory gate electrode or a length of insulating films so as to make the overlapping amount of the charge storage layer and a source region to be less than 40 nm. Therefore, in the write state, since the movement in the transverse direction of the electrons and the holes locally existing in the charge storage layer decreases, the variation of the threshold voltage when holding a high temperature can be reduced. In addition, the effective channel length is made to be 30 nm or less so as to reduce an apparent amount of holes so that coupling of the electrons with the holes in the charge storage layer decreases; therefore, the variation of the threshold voltage when holding at room temperature can be reduced.

公开(公告)号：US08390053B2

公开(公告)日：2013-03-05

申请号：US12188412

申请日：2008-08-08

申请人： Kenichi Akita ,  Daisuke Okada ,  Keisuke Kuwahara ,  Yasufumi Morimoto ,  Yasuhiro Shimamoto ,  Kan Yasui ,  Tsuyoshi Arigane ,  Tetsuya Ishimaru

发明人： Kenichi Akita ,  Daisuke Okada ,  Keisuke Kuwahara ,  Yasufumi Morimoto ,  Yasuhiro Shimamoto ,  Kan Yasui ,  Tsuyoshi Arigane ,  Tetsuya Ishimaru

IPC分类号： H01L29/792

CPC分类号： H01L29/66833 ,  H01L27/115 ,  H01L27/11563 ,  H01L27/11568 ,  H01L29/792

摘要： A charge storage layer interposed between a memory gate electrode and a semiconductor substrate is formed shorter than a gate length of the memory gate electrode or a length of insulating films so as to make the overlapping amount of the charge storage layer and a source region to be less than 40 nm. Therefore, in the write state, since the movement in the transverse direction of the electrons and the holes locally existing in the charge storage layer decreases, the variation of the threshold voltage when holding a high temperature can be reduced. In addition, the effective channel length is made to be 30 nm or less so as to reduce an apparent amount of holes so that coupling of the electrons with the holes in the charge storage layer decreases; therefore, the variation of the threshold voltage when holding at room temperature can be reduced.

摘要翻译： 插入在存储栅电极和半导体衬底之间的电荷存储层形成为比存储栅电极的栅极长度或绝缘膜的长度短，以使电荷存储层和源极区域的重叠量成为 小于40nm。 因此，在写入状态下，由于在电荷存储层中局部存在的电子和空穴的横向的移动减少，因此可以降低保持高温时的阈值电压的变化。 此外，有效沟道长度为30nm以下，以减少空穴的表观量，使得电子与电荷存储层中的空穴的耦合减小; 因此，可以降低在室温下保持时的阈值电压的变化。

公开(公告)号：US07759720B2

公开(公告)日：2010-07-20

申请号：US12273308

申请日：2008-11-18

申请人： Tsuyoshi Arigane ,  Digh Hisamoto ,  Yasuhiro Shimamoto ,  Toshiyuki Mine

发明人： Tsuyoshi Arigane ,  Digh Hisamoto ,  Yasuhiro Shimamoto ,  Toshiyuki Mine

IPC分类号： H01L29/94

CPC分类号： H01L29/42328 ,  G11C16/3418 ,  H01L27/11521 ,  H01L27/1203 ,  H01L29/7883

摘要： Provided is a nonvolatile semiconductor memory device highly integrated and highly reliable. A plurality of memory cells are formed in a plurality of active regions sectioned by a plurality of isolations (silicon oxide films) extending in the Y direction and deeper than a well (p type semiconductor region). In each memory cell, a contact is provided in the well (p type semiconductor region) so as to penetrate through a source diffusion layer (n+ type semiconductor region), and the contact that electrically connects bit lines (metal wirings) and the source diffusion layer (n+ type semiconductor region) is also electrically connected to the well (p type semiconductor region).

摘要翻译： 提供了高度集成且高度可靠的非易失性半导体存储器件。 多个存储单元形成在由在Y方向上延伸并且比阱（p型半导体区域）更深的多个隔离（氧化硅膜）分割的多个有源区域中。 在每个存储单元中，在阱（p型半导体区域）中提供接触以穿透源极扩散层（n +型半导体区域），并且将位线（金属布线）和源极扩散 层（n +型半导体区）也与阱（p型半导体区）电连接。

公开(公告)号：US07687845B2

公开(公告)日：2010-03-30

申请号：US11943909

申请日：2007-11-21

申请人： Tsuyoshi Arigane ,  Digh Hisamoto ,  Yasuhiro Shimamoto

发明人： Tsuyoshi Arigane ,  Digh Hisamoto ,  Yasuhiro Shimamoto

IPC分类号： H01L29/76 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/115 ,  G11C16/0466 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/7851

摘要： A charge trapping layer in an element isolation region and that in an isolation region between a memory transistor and a selection transistor are removed so that the charges are not injected or trapped in the regions. Also, in an element isolation region, gate electrodes of each memory transistor are united at a position higher than a gate electrode of the selection transistor from a surface of a silicon substrate in an element isolation region, thereby reducing the capacitance between the memory transistor and the selection transistor.

摘要翻译： 去除元件隔离区域中的电荷捕获层，以及在存储晶体管和选择晶体管之间的隔离区域中的电荷捕获层，使得电荷不被注入或被捕获在该区域中。 此外，在元件隔离区域中，每个存储晶体管的栅极电极从元件隔离区域中的硅衬底的表面在选择晶体管的栅电极的高位置处结合，从而减小存储晶体管和 选择晶体管。