公开(公告)号：US07190338B2

公开(公告)日：2007-03-13

申请号：US11091012

申请日：2005-03-25

申请人： Yasushi Kubota ,  Hajime Washio ,  Michael James Brownlow ,  Graham Andrew Cairns ,  Yasuyoshi Kaise ,  Kazuhiro Maeda

发明人： Yasushi Kubota ,  Hajime Washio ,  Michael James Brownlow ,  Graham Andrew Cairns ,  Yasuyoshi Kaise ,  Kazuhiro Maeda

IPC分类号： G09G5/00

CPC分类号： G09G3/2011 ,  G09G3/3648 ,  G09G3/3677 ,  G09G3/3688 ,  G09G5/005 ,  G09G5/006 ,  G09G2300/0456 ,  G09G2310/0205 ,  G09G2310/0248 ,  G09G2310/027 ,  G09G2310/0281 ,  G09G2310/0289 ,  G09G2310/0294 ,  G09G2320/0626 ,  G09G2330/021 ,  G09G2340/0428 ,  G09G2340/10 ,  G09G2340/12 ,  G09G2360/144 ,  H01L27/124 ,  H04N2007/145

摘要： An image display device includes two data signal line drive circuits and two scan signal line drive circuits configured differently from each other. Different data signal line drive circuits and scan signal line drive circuit are compatible with different display formats. A display can be produced in the most suitable display format, and power consumption also can be reduced, by switch operating drive circuits according to the kind of input video and environmental conditions. Further, an image can be written over another image by writing video signals to signal lines with a time lag using a plurality of drive circuits; therefore, a superimposed display can be produced without externally processing the video signals. Thus, both a satisfactory image display and low power consumption can be achieved in an image display device.

摘要翻译： 图像显示装置包括两个数据信号线驱动电路和彼此不同地配置的两个扫描信号线驱动电路。 不同的数据信号线驱动电路和扫描信号线驱动电路兼容不同的显示格式。 可以以最合适的显示格式生产显示器，并且可以通过根据输入视频的类型和环境条件的开关操作驱动电路来降低功耗。 此外，通过使用多个驱动电路将视频信号以时间滞后的方式写入信号线，可以在另一图像上写入图像; 因此，可以在不外部处理视频信号的情况下产生叠加显示。 因此，可以在图像显示装置中实现令人满意的图像显示和低功耗。

公开(公告)号：US06836269B2

公开(公告)日：2004-12-28

申请号：US09795658

申请日：2001-02-28

申请人： Kazuhiro Maeda ,  Hajime Washio ,  Yasushi Kubota ,  Yasuyoshi Kaise ,  Michael James Brownlow ,  Graham Andrew Cairns

发明人： Kazuhiro Maeda ,  Hajime Washio ,  Yasushi Kubota ,  Yasuyoshi Kaise ,  Michael James Brownlow ,  Graham Andrew Cairns

IPC分类号： G09G500

CPC分类号： G09G3/3688 ,  G09G2310/0248 ,  G09G2310/0289 ,  G09G2330/021

摘要： A precharge control circuit constituted by (1) a latch circuit mounted in a precharge circuit and (2) a level shifter circuit of a current drive type controlled through an output of the latch circuit is included. The precharge control circuit changes the latch circuit to an active state to cause the level shifter circuit of a current drive type to operate only during a precharge period and also during immediately preceding and succeeding periods, and outside these periods, changes the latch circuit in a non-active state and the level shifter circuit of a current drive type in an operating state to save power consumption in the level shifter circuit. This enables a low-power-consuming precharge circuit, as well as a low-power-consuming image display device with a high quality display capability, to be offered.

摘要翻译： 一种预充电控制电路，包括：（1）安装在预充电电路中的锁存电路和（2）通过锁存电路的输出控制的电流驱动型电平移位电路。 预充电控制电路将锁存电路改变为有效状态，使得电流驱动类型的电平移动电路仅在预充电期间以及在紧接之前和之后周期期间操作，并且在这些周期之外，将锁存电路改变为 非活动状态和电流驱动类型的电平移位器电路，以在电平移位器电路中节省功耗。 这使得能够提供低功耗预充电电路以及具有高质量显示能力的低功耗图像显示装置。

公开(公告)号：US06724363B1

公开(公告)日：2004-04-20

申请号：US09568889

申请日：2000-05-11

申请人： Masakazu Satoh ,  Yasushi Kubota ,  Hajime Washio ,  Kazuhiro Maeda ,  Michael James Brownlow ,  Graham Andrew Cairns

发明人： Masakazu Satoh ,  Yasushi Kubota ,  Hajime Washio ,  Kazuhiro Maeda ,  Michael James Brownlow ,  Graham Andrew Cairns

IPC分类号： G09G336

CPC分类号： G11C19/00 ,  G09G3/3674 ,  G09G3/3685 ,  G09G2310/0283 ,  G09G2310/0289 ,  G09G2330/021 ,  G11C19/28

摘要： A shift register is provided with a shift register section composed of a plurality of stages of flip-flops that operate in synchronization with a clock signal, and level shifters for boosting a start signal lower than a driving voltage and for applying the same to both ends of the shift register section, and the shift register is capable of switching the shift direction in accordance with the switching signal. The foregoing level shifters are current-driving-type level shifters that can operate even in the case where the transistor characteristics are inferior or in the case of fast operations, and that can carry out level shifting even with a start signal having a small amplitude. Furthermore, the foregoing level shifters are provided at both ends of the shift register section, respectively, and one of the same stops operating in accordance with a switching signal, so that consumed power should decrease. Consequently, there can be provided a shift register that is capable of shifting in two directions, that can normally operate even with an input signal having a small amplitude, and that therefore consumes less electric power.

公开(公告)号：US06617878B2

公开(公告)日：2003-09-09

申请号：US10216347

申请日：2002-08-09

申请人： Michael James Brownlow ,  Graham Andrew Cairns ,  Yasushi Kubota ,  Hajime Washio

发明人： Michael James Brownlow ,  Graham Andrew Cairns ,  Yasushi Kubota ,  Hajime Washio

IPC分类号： H03K190175

CPC分类号： H03K3/356113

摘要： A voltage level shifter comprises an input stage in the form of cross-coupled source followers and an output stage in the form of an amplifier AMP, which may have single-ended or differential inputs. The source followers comprise the transistors M1 and M2 and the transistors M3 and M4. Differential inputs IN and !IN are connected to the gates of the transistors M2 and M4. A bias voltage is supplied to the gate of the transistor M1 from a node B to which the drain of the transistor M3 and the source of the transistor M4 are connected. Similarly, a bias voltage is supplied to the gate of the transistor M3 from a node A to which the drain of the transistor M1 and the source of the transistor M2 are connected.

公开(公告)号：US06559824B1

公开(公告)日：2003-05-06

申请号：US09666376

申请日：2000-09-20

申请人： Yasushi Kubota ,  Hajime Washio ,  Kazuhiro Maeda ,  Graham Andrew Cairns ,  Michael James Brownlow

发明人： Yasushi Kubota ,  Hajime Washio ,  Kazuhiro Maeda ,  Graham Andrew Cairns ,  Michael James Brownlow

IPC分类号： G09G336

CPC分类号： G09G3/3688 ,  G09G3/20 ,  G09G3/3677 ,  G09G2300/0408 ,  G09G2310/0232 ,  G09G2310/0248 ,  G09G2310/0289 ,  G09G2330/021

摘要： A matrix type image display device has a structure in which the internal states of all of shift registers (the outputs of flip-flops included in the shift registers) in a scanning signal line drive circuit and data signal line drive circuit are made inactive by the use of an initializing signal generated by a NAND gate based on a combination of signals, which do not affect a displayed image, from a control circuit. With this structure, since the shift registers are initialized when power is supplied, it is possible to prevent an indefinite state when power is supplied. Therefore, by selectively inputting signals (such as clock signals) for controlling the shift registers, it is possible to prevent an excessive increase in the signal line load. Consequently, the operation of the image display device can be stabilized. Moreover, it is not necessary to improve the drive ability of an external IC incorporating the control circuit and the supply ability of a power supply circuit, thereby achieving a reduction in the cost and power consumption of the external IC.

摘要翻译： 矩阵型图像显示装置具有这样的结构，其中扫描信号线驱动电路和数据信号线驱动电路中的所有移位寄存器（包括在移位寄存器中的触发器的输出）的内部状态由 基于不影响显示图像的信号的组合，从NAND门产生的初始化信号从控制电路使用。 利用这种结构，由于在供电时初始化了移位寄存器，所以可以在供电时防止不确定的状态。 因此，通过选择性地输入用于控制移位寄存器的信号（例如时钟信号），可以防止信号线负载的过度增加。 因此，能够使图像显示装置的动作稳定。 此外，不需要提高包含控制电路的外部IC的驱动能力和电源电路的供给能力，从而实现了外部IC的成本和功耗的降低。

公开(公告)号：US06724361B1

公开(公告)日：2004-04-20

申请号：US09703918

申请日：2000-11-01

申请人： Hajime Washio ,  Yasushi Kubota ,  Kazuhiro Maeda ,  Yasuyoshi Kaise ,  Michael James Brownlow ,  Graham Andrew Cairns

发明人： Hajime Washio ,  Yasushi Kubota ,  Kazuhiro Maeda ,  Yasuyoshi Kaise ,  Michael James Brownlow ,  Graham Andrew Cairns

IPC分类号： G09G336

CPC分类号： G09G3/3677 ,  G09G3/3688 ,  G09G2310/0289

摘要： In a shift register provided with flip-flops that operate in synchronism with a clock signal, and a switching means, which is opened and closed in response to an output of the preceding stage of each of the flip-flops, is installed. The clock signal is selectively inputted by the switching means, and the selected clock signal is inverted and used as a shift register output from each of the stages. An output pulse having the same width as the pulse of the clock signal is generated.

摘要翻译： 在设置有与时钟信号同步工作的触发器的移位寄存器中，并且响应于每个触发器的前级的输出而被打开和关闭的开关装置被安装。 时钟信号由切换装置选择性地输入，所选择的时钟信号被反相并用作从每个级输出的移位寄存器。 产生具有与时钟信号的脉冲相同宽度的输出脉冲。

公开(公告)号：US06476637B1

公开(公告)日：2002-11-05

申请号：US09568892

申请日：2000-05-11

申请人： Michael James Brownlow ,  Graham Andrew Cairns ,  Yasushi Kubota ,  Hajime Washio

发明人： Michael James Brownlow ,  Graham Andrew Cairns ,  Yasushi Kubota ,  Hajime Washio

IPC分类号： H03K190175

CPC分类号： H03K3/356113

摘要： A voltage level shifter comprises an input stage in the form of cross-coupled source followers and an output stage in the form of an amplifier AMP, which may have single-ended or differential inputs. The source followers comprise the transistors M1 and M2 and the transistors M3 and M4. Differential inputs IN and !IN are connected to the gates of the transistors M2 and M4. A bias voltage is supplied to the gate of the transistor M1 from a node B to which the drain of the transistor M3 and the source of the transistor M4 are connected. Similarly, a bias voltage is supplied to the gate of the transistor M3 from a node A to which the drain of the transistor M1 and the source of the transistor M2 are connected.

摘要翻译： 电压电平移位器包括交叉耦合源跟随器形式的输入级和放大器AMP形式的输出级，其可以具有单端或差分输入。 源极跟随器包括晶体管M1和M2以及晶体管M3和M4。 差分输入IN和！IN连接到晶体管M2和M4的栅极。 从晶体管M3的漏极和晶体管M4的源极连接的节点B向晶体管M1的栅极提供偏置电压。 类似地，偏置电压从晶体管M1的漏极和晶体管M2的源极连接到的节点A提供给晶体管M3的栅极。

公开(公告)号：US06262598B1

公开(公告)日：2001-07-17

申请号：US09517984

申请日：2000-03-03

申请人： Graham Andrew Cairns ,  Michael James Brownlow ,  Yasushi Kubota ,  Hajime Washio

发明人： Graham Andrew Cairns ,  Michael James Brownlow ,  Yasushi Kubota ,  Hajime Washio

IPC分类号： H03K190175

CPC分类号： G11C7/062 ,  H03K19/018521 ,  H03K19/018528 ,  H03K19/01855

摘要： A voltage level shifter comprises complementary transistors T1, T2 connected between a supply line vdd and an inverting input !IN. The gate of the transistor T1 is connected to a direct signal input IN whereas the gate of the transistor T2 receives a shifted version of the direct input signal from a source-follower comprising the transistors T3 and T4. The level shifter may also be embodied as a differential cross-coupled sense amplifier with the sources of the drain load transistors being crossed coupled to the differential inputs.

摘要翻译： 电压电平移位器包括连接在电源线vdd和反相输入端IN之间的互补晶体管T1，T2。 晶体管T1的栅极连接到直接信号输入IN，而晶体管T2的栅极接收来自包括晶体管T3和T4的源极跟随器的直接输入信号的偏移版本。 电平移位器还可以被实现为差分交叉耦合读出放大器，其中漏极负载晶体管的源极与差分输入交叉耦合。

公开(公告)号：US08354990B2

公开(公告)日：2013-01-15

申请号：US12087870

申请日：2007-01-29

申请人： Gareth John ,  Patrick Zebedee ,  Michael James Brownlow ,  Tim Gasser ,  Jeremy Lock ,  Graham Andrew Cairns ,  Jaganath Rajendra ,  Harry Garth Walton

发明人： Gareth John ,  Patrick Zebedee ,  Michael James Brownlow ,  Tim Gasser ,  Jeremy Lock ,  Graham Andrew Cairns ,  Jaganath Rajendra ,  Harry Garth Walton

IPC分类号： G09G3/36

CPC分类号： H03K17/063 ,  G09G3/3688 ,  G09G2310/027 ,  G09G2310/0286 ,  G09G2310/0289 ,  G11C19/184

摘要： In one embodiment of the present invention, a drive circuit includes: a logic block connected between a source of a first voltage and a source of a second voltage, and a sampler including a plurality of sampling circuits. Each sampling circuit is for sampling, in use, an input data signal and outputting a voltage to a respective output. The drive circuit further includes a voltage booster having plurality of voltage boost circuits, each voltage boost circuit being associated with a respective one of the sampling circuits and, in use, generating a boosted voltage signal and providing the boosted voltage signal to the respective sampling circuit. Each voltage boost circuit is connected between the source of the first voltage and the source of the second voltage. The logic block may be, but is not limited to, a shift register.

摘要翻译： 在本发明的一个实施例中，驱动电路包括：连接在第一电压源和第二电压源之间的逻辑块，以及包括多个采样电路的采样器。 每个采样电路用于在使用中对输入数据信号进行采样，并将电压输出到相应的输出。 驱动电路还包括具有多个升压电路的升压电路，每个升压电路与相应的一个采样电路相关联，并且在使用中产生升压电压信号并将升压电压信号提供给相应的采样电路 。 每个升压电路连接在第一电压源和第二电压源之间。 逻辑块可以是但不限于移位寄存器。

公开(公告)号：US06970163B2

公开(公告)日：2005-11-29

申请号：US10092372

申请日：2002-03-05

申请人： Graham Andrew Cairns ,  Michael James Brownlow

发明人： Graham Andrew Cairns ,  Michael James Brownlow

IPC分类号： G02F1/133 ,  G09G3/20 ,  G09G3/36 ,  G09G5/00 ,  G09G5/18

CPC分类号： G09G3/20 ,  G09G3/3648 ,  G09G5/006 ,  G09G5/18 ,  G09G2300/0408 ,  G09G2320/0276 ,  G09G2320/103 ,  G09G2330/021 ,  G09G2330/022 ,  G09G2340/0435

摘要： A frame rate controller (20) is provided for controlling the frame refresh rate of an active matrix display. The controller (20) comprises a first circuit such as a preloadable synchronous counter (21) which counts vertical synchronization signals VSYNC and supplies an enable signal FE for every Nth frame of data, where N is an integer greater than zero and is selectable. A gating arrangement (26) is controlled by the enable signal FE so that an active matrix display is refreshed for every Nth frame of data, thus allowing a reduction in power consumption of the display.

摘要翻译： 提供了一种用于控制有源矩阵显示器的帧刷新率的帧速率控制器（20）。 控制器（20）包括第一电路，例如对可垂直同步信号VSYNC进行计数的预加载同步计数器（21），并为每第N个数据帧提供使能信号FE，其中N是大于零的整数并且是可选择的。 选通布置（26）由使能信号FE控制，使得对于每第N帧数据刷新有源矩阵显示，从而允许显示器的功耗降低。