公开(公告)号：US5983331A

公开(公告)日：1999-11-09

申请号：US943411

申请日：1997-09-30

申请人： Hironori Akamatsu ,  Toshio Yamada ,  Hisakazu Kotani ,  Yoshiro Nakata

发明人： Hironori Akamatsu ,  Toshio Yamada ,  Hisakazu Kotani ,  Yoshiro Nakata

IPC分类号： G06F15/78 ,  G11C11/401 ,  G06F12/00

CPC分类号： G06F15/7832

摘要： A CPU acting as a mother chip, in combination with a DRAM acting as a subsidiary chip, is mounted. A mode output circuit is able to set the storage capacity of the DRAM as well as the refresh cycle of the DRAM for forwarding to a mode input circuit of the CPU through a mode output terminal of the DRAM and a mode input terminal of the CPU. The CPU controls an address generator according to the data from the mode input circuit, to set the number of bits of address data for access to the DRAM according to the DRAM storage capacity and the DRAM refresh cycle.

摘要翻译： 作为母芯片的CPU与作为辅助芯片的DRAM组合安装。 模式输出电路能够设置DRAM的存储容量以及用于通过DRAM的模式输出端和CPU的模式输入端转发到CPU的模式输入电路的DRAM的刷新周期。 CPU根据来自模式输入电路的数据控制地址生成器，根据DRAM存储容量和DRAM刷新周期设定用于存取DRAM的地址数据的位数。

公开(公告)号：US5764566A

公开(公告)日：1998-06-09

申请号：US893682

申请日：1997-07-11

申请人： Hironori Akamatsu ,  Toru Iwata ,  Hisakazu Kotani

发明人： Hironori Akamatsu ,  Toru Iwata ,  Hisakazu Kotani

IPC分类号： G11C11/412 ,  G11C11/417 ,  G11C11/413

CPC分类号： G11C11/412 ,  G11C11/417

摘要： When a memory chip is in a standby mode, a ground power supply line of a flip-flop forming a memory cell is intermittently placed in the floating state. A switching NMOS transistor is connected between the ground power supply line and a power supply VSS. The gate of the NMOS transistor is controlled by an activation signal. When entering the floating state, the ground power supply line is charged due to an off-leakage current flowing in the transistor of the memory cell. As a result, the voltage of the ground power supply line is increased from the voltage of the power supply VSS. Accordingly, the off-leakage current of the memory cell is reduced, whereby the standby-time power consumption of the memory chip is decreased. When the voltage of the ground power supply line keeps going up, it becomes impossible to read data held in the memory cell in a short time, resulting in the data being lost. In order to prevent the loss of the data, the switching NMOS transistor is made to intermittently turn on.

摘要翻译： 当存储器芯片处于待机模式时，形成存储单元的触发器的接地电源线被间歇地置于浮置状态。 开关NMOS晶体管连接在接地电源线和电源VSS之间。 NMOS晶体管的栅极由激活信号控制。 当进入浮动状态时，由于在存储单元的晶体管中流过的漏电流导致接地电源线被充电。 结果，接地电源线的电压从电源VSS的电压增加。 因此，存储单元的泄漏电流减小，从而存储芯片的待机时功耗降低。 当接地电源线的电压持续上升时，不可能在短时间内读取保存在存储单元中的数据，导致数据丢失。 为了防止数据丢失，使开关式NMOS晶体管间歇地导通。

公开(公告)号：US5699300A

公开(公告)日：1997-12-16

申请号：US341947

申请日：1994-11-16

申请人： Hironori Akamatsu ,  Tsuyoshi Shiragasawa ,  Junko Matsushima ,  Hisakazu Kotani

发明人： Hironori Akamatsu ,  Tsuyoshi Shiragasawa ,  Junko Matsushima ,  Hisakazu Kotani

IPC分类号： G11C11/401 ,  G11C7/10 ,  G11C8/14 ,  G11C8/18 ,  G11C11/409 ,  G11C7/00 ,  G11C8/00

CPC分类号： G11C7/1015 ,  G11C8/14 ,  G11C8/18

摘要： A semiconductor memory device comprising memory cells arranged in a matrix with plural pairs of bit lines to be column addressed and connected to sense amplifiers, and word lines to be row addressed and divided into divisional word lines. Output signals of sense amplifiers selected by the column addressing are transferred to respective data lines. The divisional word lines are time-sequentially activated corresponding to the row addressing with the activated states of any two sequential divisional word lines overlapped for a fractional time of the full activation time. The sense amplifiers are grouped into plural groups with respective common column addresses. Each group of sense amplifiers have their outputs to be applied to respective data lines connected to a serial/parallel converter.

摘要翻译： 一种半导体存储器件，包括以矩阵形式布置的存储器单元，其中多对位线被列地址并连接到读出放大器，并且字线被行寻址并分成划分字线。 由列寻址选择的读出放大器的输出信号被传送到相应的数据线。 分割字线对应于行寻址而被时间顺序地激活，其中任何两个连续分割字线的激活状态在完全激活时间的分数时间内重叠。 感测放大器被分组成具有相应公共列地址的多个组。 每组读出放大器的输出都被施加到连接到串行/并行转换器的相应数据线上。

公开(公告)号：US6023440A

公开(公告)日：2000-02-08

申请号：US320577

申请日：1999-05-27

申请人： Hisakazu Kotani ,  Hironori Akamatsu ,  Tsutomu Fujita

发明人： Hisakazu Kotani ,  Hironori Akamatsu ,  Tsutomu Fujita

IPC分类号： G09G5/39 ,  G11C11/406 ,  G11C13/00

CPC分类号： G09G5/39 ,  G11C11/406 ,  G09G2360/123 ,  G09G5/001

摘要： A memory array divided into a plurality of sub-memory-arrays is disposed on a chip so that, if a specified sub-memory-array is selected by a sub-memory-array selecting circuit, a normal read/write operation is performed with respect to the sub-memory-array based on an address indicated by a group of external address signals. At the same time, a clock generator for self-refresh mounted on a chip generates a word-line basic clock for self-refresh and a word-line basic clock for refresh, thereby selecting the word lines in the sub-memory-arrays which have not been selected. Prior to a predetermined time at which the sub-memory-array subjected to a refresh operation is subsequently selected, a refresh halt signal is outputted so as to forcibly halt the refresh operation, thereby preventing insufficient recharging of a memory cell. Each of the plurality of sub-memory-arrays stores, of sequential sets of image data, data on one frame or one field.

摘要翻译： 分割成多个子存储器阵列的存储器阵列设置在芯片上，使得如果通过子存储器阵列选择电路选择了指定的子存储器阵列，则执行正常的读取/写入操作， 基于由一组外部地址信号指示的地址对子存储器阵列。 同时，安装在芯片上的用于自刷新的时钟发生器产生用于自刷新的字线基本时钟和用于刷新的字线基本时钟，从而选择子存储阵列中的字线，其中 尚未选中。 在随后选择进行刷新操作的子存储阵列的预定时间之前，输出刷新停止信号，以强制中止刷新操作，从而防止存储单元的充电不足。 多个子存储器阵列中的每一个存储顺序的图像数据组，一帧或一个场上的数据。

公开(公告)号：US5999022A

公开(公告)日：1999-12-07

申请号：US631914

申请日：1996-04-15

申请人： Toru Iwata ,  Hironori Akamatsu ,  Hisakazu Kotani ,  Hiroyuki Yamauchi ,  Akira Matsuzawa ,  Shoichiro Tada

发明人： Toru Iwata ,  Hironori Akamatsu ,  Hisakazu Kotani ,  Hiroyuki Yamauchi ,  Akira Matsuzawa ,  Shoichiro Tada

IPC分类号： H03K19/00 ,  H03K19/0185 ,  H03K3/00

CPC分类号： H03K19/01855 ,  H03K19/0016

摘要： A driver circuit which drives a signal line includes a first output section for outputting a reference voltage potential to the signal line during a first period and a second output section for outputting one of a first information voltage potential and a second information voltage potential in accordance with an input signal during a second period.

摘要翻译： 驱动信号线的驱动器电路包括：第一输出部，用于在第一时段期间向信号线输出参考电压电位;以及第二输出部，用于输出第一信息电压电位和第二信息电压电位之一 在第二时段期间的输入信号。

公开(公告)号：US5805524A

公开(公告)日：1998-09-08

申请号：US593851

申请日：1996-01-30

申请人： Hisakazu Kotani ,  Hironori Akamatsu ,  Tsutomu Fujita

发明人： Hisakazu Kotani ,  Hironori Akamatsu ,  Tsutomu Fujita

IPC分类号： G09G5/39 ,  G11C11/406 ,  G11C13/00

CPC分类号： G09G5/39 ,  G11C11/406 ,  G09G2360/123 ,  G09G5/001

摘要： A memory array divided into a plurality of sub-memory-arrays is disposed on a chip so that, if a specified sub-memory-array is selected by a sub-memory-array selecting circuit, a normal read/write operation is performed with respect to the sub-memory-array based on an address indicated by a group of external address signals. At the same time, a clock generator for self-refresh mounted on a chip generates a word-line basic clock for self-refresh and a word-line basic clock for refresh, thereby selecting the word lines in the sub-memory-arrays which have not been selected. Prior to a predetermined time at which the sub-memory-array subjected to a refresh operation is subsequently selected, a refresh halt signal is outputted so as to forcibly halt the refresh operation, thereby preventing insufficient recharging of a memory cell. Each of the plurality of sub-memory-arrays stores, of sequential sets of image data, data on one frame or one field.

公开(公告)号：US5293339A

公开(公告)日：1994-03-08

申请号：US863268

申请日：1992-04-03

申请人： Toshikazu Suzuki ,  Hisakazu Kotani ,  Hironori Akamatsu

发明人： Toshikazu Suzuki ,  Hisakazu Kotani ,  Hironori Akamatsu

IPC分类号： G11C29/00 ,  G11C29/04 ,  G11C8/00 ,  H03K19/003

CPC分类号： G11C29/806 ,  G11C29/83 ,  G11C29/84

摘要： A semiconductor integrated circuit contains a plurality of programmable circuits each including a plurality of fuses and a first transistor which has a gate subjected to an address decoded signal, a drain connected to first ends of the fuses, and a source connected to a common precharge node. The address decoded signal results from decoding a first portion of an address signal for access to memory cells. The sources of the first transistors in the respective programmable circuits are connected to the common precharge node. A plurality of second transistors have gates subjected to a second portion of the address signal, sources connected to a first power supply line, and drains connected to second ends of the fuses in each of the programmable circuits respectively. The second portion of the address signal differs from the first portion of the address signal. A third transistor has a gate subjected to a precharge control signal, a source connected to a second power supply line, and a drain connected to the common precharge node.

摘要翻译： 半导体集成电路包含多个可编程电路，每个可编程电路包括多个保险丝，第一晶体管具有经过地址解码信号的栅极，连接到保险丝的第一端的漏极和连接到公共预充电节点 。 地址解码信号是对解码访问存储单元的地址信号的第一部分而产生的。 各个可编程电路中的第一晶体管的源极连接到公共预充电节点。 多个第二晶体管具有经过地址信号的第二部分的栅极，分别连接到第一电源线的源和连接到每个可编程电路中的熔丝的第二端的漏极。 地址信号的第二部分与地址信号的第一部分不同。 第三晶体管具有经受预充电控制信号的栅极，连接到第二电源线的源极和连接到公共预充电节点的漏极。

公开(公告)号：US5555527A

公开(公告)日：1996-09-10

申请号：US358606

申请日：1994-12-14

申请人： Hisakazu Kotani ,  Hironori Akamatsu ,  Tsutomu Fujita

发明人： Hisakazu Kotani ,  Hironori Akamatsu ,  Tsutomu Fujita

IPC分类号： G09G5/39 ,  G11C11/406 ,  G11C13/00

CPC分类号： G09G5/39 ,  G11C11/406 ,  G09G2360/123 ,  G09G5/001

摘要： A memory array divided into a plurality of sub-memory-arrays is disposed on a chip so that, if a specified sub-memory-array is selected by a sub-memory-array selecting circuit, a normal read/write operation is performed with respect to the sub-memory-array based on an address indicated by a group of external address signals. At the same time, a clock generator for self-refresh mounted on a chip generates a word-line basic clock for self-refresh and a word-line basic clock for refresh, thereby selecting the word lines in the sub-memory-arrays which have not been selected. Prior to a predetermined time at which the sub-memory-array subjected to a refresh operation is subsequently selected, a refresh halt signal is outputted so as to forcibly halt the refresh operation, thereby preventing insufficient recharging of a memory cell. Each of the plurality of sub-memory-arrays stores, of sequential sets of image data, data on one frame or one field.

公开(公告)号：US5949733A

公开(公告)日：1999-09-07

申请号：US3821

申请日：1998-01-07

申请人： Hisakazu Kotani ,  Hironori Akamatsu ,  Tsutomu Fujita

发明人： Hisakazu Kotani ,  Hironori Akamatsu ,  Tsutomu Fujita

IPC分类号： G09G5/39 ,  G11C11/406 ,  G11C13/00

CPC分类号： G09G5/39 ,  G11C11/406 ,  G09G2360/123 ,  G09G5/001

摘要： A memory array divided into a plurality of sub-memory-arrays is disposed on a chip so that, if a specified sub-memory-array is selected by a sub-memory-array selecting circuit, a normal read/write operation is performed with respect to the sub-memory-array based on an address indicated by a group of external address signals. At the same time, a clock generator for self-refresh mounted on a chip generates a word-line basic clock for self-refresh and a word-line basic clock for refresh, thereby selecting the word lines in the sub-memory-arrays which have not been selected. Prior to a predetermined time at which the sub-memory-array subjected to a refresh operation is subsequently selected, a refresh halt signal is outputted so as to forcibly halt the refresh operation, thereby preventing insufficient recharging of a memory cell. Each of the plurality of sub-memory-arrays stores, of sequential sets of image data, data on one frame or one field.

公开(公告)号：US5854767A

公开(公告)日：1998-12-29

申请号：US548671

申请日：1995-10-26

申请人： Kazuyoshi Nishi ,  Hironori Akamatsu ,  Toshiaki Tsuji ,  Hisakazu Kotani

发明人： Kazuyoshi Nishi ,  Hironori Akamatsu ,  Toshiaki Tsuji ,  Hisakazu Kotani

IPC分类号： G11C7/10 ,  G11C7/00

CPC分类号： G11C7/103

摘要： A semiconductor memory device according to the present invention includes a plurality of blocks. A plurality of first selection signals, second selection signals, and third selection signals are provided to the blocks. Each block includes: a memory cell array; a read/write circuit for simultaneously reading out a plurality of data from the memory cell array and subsequently simultaneously writing a plurality of further data into the memory cell array when the corresponding first selection signal is active; a parallel/serial conversion circuit for outputting the plurality of simultaneously read out data, the outputting being performed data by data in a serial manner along the time axis; a transfer gate for a reading operation controlled by the corresponding second selection signal, the gate outputting the plurality of data from the parallel/serial conversion circuit when the corresponding second selection signal is active; a serial/parallel conversion circuit for receiving the plurality of further data, the further data being sequential, and for outputting the plurality of sequential data to the read/write circuit in a parallel manner along the time axis; and a transfer gate for a writing operation controlled by the corresponding third selection signal, the gate outputting the plurality of sequential data to the serial/parallel conversion circuit when the corresponding third selection signal is active. Only one second selection signal is allowed to be active at a given time, while the other remain non-active. Only one third selection signal is allowed to be active at a given time, while the other remain non-active.

摘要翻译： 根据本发明的半导体存储器件包括多个块。 多个第一选择信号，第二选择信号和第三选择信号被提供给块。 每个块包括：存储单元阵列; 读/写电路，用于从存储单元阵列同时读出多个数据，随后当对应的第一选择信号有效时，随后将多个另外的数据写入存储单元阵列; 用于输出多个同时读出的数据的并行/串行转换电路，所述输出是沿着时间轴以串行方式的数据进行数据的; 用于由相应的第二选择信号控制的读取操作的传输门，当对应的第二选择信号有效时，门从并行/串行转换电路输出多个数据; 用于接收多个另外的数据的串行/并行转换电路，所述另外的数据是顺序的，并且用于沿着时间轴并行地将多个顺序数据输出到读/写电路; 以及用于由对应的第三选择信号控制的写入操作的传输门，当对应的第三选择信号有效时，门将串行/并行转换电路输出到串行/并行转换电路。 在给定的时间只允许一秒钟的选择信号被激活，而另一个选择信号保持不活动。 在给定的时间只允许有三分之一的选择信号被激活，而另一个则保持不活动。