利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

80 条记录 (耗时 0.036 秒)

    Semiconductor memory, moving-picture storing memory, moving-picture storing apparatus, moving-picture displaying apparatus, static-picture storing memory, and electronic notebook
    2.
    发明授权
    Semiconductor memory, moving-picture storing memory, moving-picture storing apparatus, moving-picture displaying apparatus, static-picture storing memory, and electronic notebook 失效
    半导体存储器，运动图像存储存储器，运动图像存储装置，运动图像显示装置，静态图像存储存储器和电子笔记本

    公开(公告)号：US6023440A

    公开(公告)日：2000-02-08

    申请号：US320577

    申请日：1999-05-27

    申请人： Hisakazu Kotani ,  Hironori Akamatsu ,  Tsutomu Fujita

    发明人： Hisakazu Kotani ,  Hironori Akamatsu ,  Tsutomu Fujita

    IPC分类号： G09G5/39 ,  G11C11/406 ,  G11C13/00

    CPC分类号： G09G5/39 ,  G11C11/406 ,  G09G2360/123 ,  G09G5/001

    摘要： A memory array divided into a plurality of sub-memory-arrays is disposed on a chip so that, if a specified sub-memory-array is selected by a sub-memory-array selecting circuit, a normal read/write operation is performed with respect to the sub-memory-array based on an address indicated by a group of external address signals. At the same time, a clock generator for self-refresh mounted on a chip generates a word-line basic clock for self-refresh and a word-line basic clock for refresh, thereby selecting the word lines in the sub-memory-arrays which have not been selected. Prior to a predetermined time at which the sub-memory-array subjected to a refresh operation is subsequently selected, a refresh halt signal is outputted so as to forcibly halt the refresh operation, thereby preventing insufficient recharging of a memory cell. Each of the plurality of sub-memory-arrays stores, of sequential sets of image data, data on one frame or one field.

    摘要翻译： 分割成多个子存储器阵列的存储器阵列设置在芯片上，使得如果通过子存储器阵列选择电路选择了指定的子存储器阵列，则执行正常的读取/写入操作， 基于由一组外部地址信号指示的地址对子存储器阵列。 同时，安装在芯片上的用于自刷新的时钟发生器产生用于自刷新的字线基本时钟和用于刷新的字线基本时钟，从而选择子存储阵列中的字线，其中 尚未选中。 在随后选择进行刷新操作的子存储阵列的预定时间之前，输出刷新停止信号，以强制中止刷新操作，从而防止存储单元的充电不足。 多个子存储器阵列中的每一个存储顺序的图像数据组，一帧或一个场上的数据。

    Static random access memory capable of reducing stendly power consumption and off-leakage current
    5.
    发明授权
    Static random access memory capable of reducing stendly power consumption and off-leakage current 失效
    静态随机存取存储器能够降低待机功耗和漏电流

    公开(公告)号：US5764566A

    公开(公告)日：1998-06-09

    申请号：US893682

    申请日：1997-07-11

    申请人： Hironori Akamatsu ,  Toru Iwata ,  Hisakazu Kotani

    发明人： Hironori Akamatsu ,  Toru Iwata ,  Hisakazu Kotani

    IPC分类号： G11C11/412 ,  G11C11/417 ,  G11C11/413

    CPC分类号： G11C11/412 ,  G11C11/417

    摘要： When a memory chip is in a standby mode, a ground power supply line of a flip-flop forming a memory cell is intermittently placed in the floating state. A switching NMOS transistor is connected between the ground power supply line and a power supply VSS. The gate of the NMOS transistor is controlled by an activation signal. When entering the floating state, the ground power supply line is charged due to an off-leakage current flowing in the transistor of the memory cell. As a result, the voltage of the ground power supply line is increased from the voltage of the power supply VSS. Accordingly, the off-leakage current of the memory cell is reduced, whereby the standby-time power consumption of the memory chip is decreased. When the voltage of the ground power supply line keeps going up, it becomes impossible to read data held in the memory cell in a short time, resulting in the data being lost. In order to prevent the loss of the data, the switching NMOS transistor is made to intermittently turn on.

    摘要翻译： 当存储器芯片处于待机模式时，形成存储单元的触发器的接地电源线被间歇地置于浮置状态。 开关NMOS晶体管连接在接地电源线和电源VSS之间。 NMOS晶体管的栅极由激活信号控制。 当进入浮动状态时，由于在存储单元的晶体管中流过的漏电流导致接地电源线被充电。 结果，接地电源线的电压从电源VSS的电压增加。 因此，存储单元的泄漏电流减小，从而存储芯片的待机时功耗降低。 当接地电源线的电压持续上升时，不可能在短时间内读取保存在存储单元中的数据，导致数据丢失。 为了防止数据丢失，使开关式NMOS晶体管间歇地导通。

    Divided wordline memory arrangement having overlapping activation of wordlines during continuous access cycle
    7.
    发明授权
    Divided wordline memory arrangement having overlapping activation of wordlines during continuous access cycle 失效
    分割的字线存储器布置在连续访问周期期间具有字线重叠的激活

    公开(公告)号：US5699300A

    公开(公告)日：1997-12-16

    申请号：US341947

    申请日：1994-11-16

    申请人： Hironori Akamatsu ,  Tsuyoshi Shiragasawa ,  Junko Matsushima ,  Hisakazu Kotani

    发明人： Hironori Akamatsu ,  Tsuyoshi Shiragasawa ,  Junko Matsushima ,  Hisakazu Kotani

    IPC分类号： G11C11/401 ,  G11C7/10 ,  G11C8/14 ,  G11C8/18 ,  G11C11/409 ,  G11C7/00 ,  G11C8/00

    CPC分类号： G11C7/1015 ,  G11C8/14 ,  G11C8/18

    摘要： A semiconductor memory device comprising memory cells arranged in a matrix with plural pairs of bit lines to be column addressed and connected to sense amplifiers, and word lines to be row addressed and divided into divisional word lines. Output signals of sense amplifiers selected by the column addressing are transferred to respective data lines. The divisional word lines are time-sequentially activated corresponding to the row addressing with the activated states of any two sequential divisional word lines overlapped for a fractional time of the full activation time. The sense amplifiers are grouped into plural groups with respective common column addresses. Each group of sense amplifiers have their outputs to be applied to respective data lines connected to a serial/parallel converter.

    摘要翻译： 一种半导体存储器件，包括以矩阵形式布置的存储器单元，其中多对位线被列地址并连接到读出放大器，并且字线被行寻址并分成划分字线。 由列寻址选择的读出放大器的输出信号被传送到相应的数据线。 分割字线对应于行寻址而被时间顺序地激活，其中任何两个连续分割字线的激活状态在完全激活时间的分数时间内重叠。 感测放大器被分组成具有相应公共列地址的多个组。 每组读出放大器的输出都被施加到连接到串行/并行转换器的相应数据线上。

    Semiconductor integrated circuit containing redundant memory element
    10.
    发明授权
    Semiconductor integrated circuit containing redundant memory element 失效
    包含冗余存储元件的半导体集成电路

    公开(公告)号：US5293339A

    公开(公告)日：1994-03-08

    申请号：US863268

    申请日：1992-04-03

    申请人： Toshikazu Suzuki ,  Hisakazu Kotani ,  Hironori Akamatsu

    发明人： Toshikazu Suzuki ,  Hisakazu Kotani ,  Hironori Akamatsu

    IPC分类号： G11C29/00 ,  G11C29/04 ,  G11C8/00 ,  H03K19/003

    CPC分类号： G11C29/806 ,  G11C29/83 ,  G11C29/84

    摘要： A semiconductor integrated circuit contains a plurality of programmable circuits each including a plurality of fuses and a first transistor which has a gate subjected to an address decoded signal, a drain connected to first ends of the fuses, and a source connected to a common precharge node. The address decoded signal results from decoding a first portion of an address signal for access to memory cells. The sources of the first transistors in the respective programmable circuits are connected to the common precharge node. A plurality of second transistors have gates subjected to a second portion of the address signal, sources connected to a first power supply line, and drains connected to second ends of the fuses in each of the programmable circuits respectively. The second portion of the address signal differs from the first portion of the address signal. A third transistor has a gate subjected to a precharge control signal, a source connected to a second power supply line, and a drain connected to the common precharge node.

    摘要翻译： 半导体集成电路包含多个可编程电路，每个可编程电路包括多个保险丝，第一晶体管具有经过地址解码信号的栅极，连接到保险丝的第一端的漏极和连接到公共预充电节点 。 地址解码信号是对解码访问存储单元的地址信号的第一部分而产生的。 各个可编程电路中的第一晶体管的源极连接到公共预充电节点。 多个第二晶体管具有经过地址信号的第二部分的栅极，分别连接到第一电源线的源和连接到每个可编程电路中的熔丝的第二端的漏极。 地址信号的第二部分与地址信号的第一部分不同。 第三晶体管具有经受预充电控制信号的栅极，连接到第二电源线的源极和连接到公共预充电节点的漏极。