公开(公告)号：US07839678B2

公开(公告)日：2010-11-23

申请号：US12560503

申请日：2009-09-16

Applicant: Hitoshi Shiga

Inventor： Hitoshi Shiga

IPC: G11C11/34

CPC classification number: G11C11/5628 ,  G11C8/08 ,  G11C16/0483 ,  G11C16/3418 ,  G11C2211/5621 ,  G11C2211/5641

Abstract: A NAND type flash memory includes first to third memory cell transistors having current paths connected in series between one end of a current path of each of first and second selection transistors, and each having a control gate and a charge storage layer, the first and second memory cell transistors being adjacent to the first and second selection transistors, the third memory cell transistor being positioned between the first and second memory cell transistors, the third memory cell transistor holding data having not less than three bits, the first memory cell transistor holding 2-bit data in which middle and upper pages is written by skipping a lower page, and a lower page verify voltage being set when writing the middle page, and a middle page verify voltage is set when writing the upper page, changing a position of a threshold distribution of the first memory cell transistor.

Abstract translation: NAND型闪存包括第一至第三存储单元晶体管，其具有串联连接在第一和第二选择晶体管中的每一个的电流路径的一端之间的电流路径，并且每个存储单元晶体管具有控制栅极和电荷存储层，第一和第二 存储单元晶体管与第一和第二选择晶体管相邻，第三存储单元晶体管位于第一和第二存储单元晶体管之间，第三存储单元晶体管保持具有不少于3位的数据，第一存储单元晶体管保持2 通过跳过下页来写入中间页和上页的位数数据，以及写入中间页时设置的下页验证电压，并且在写入上页时设置中间页验证电压，改变位置 第一存储单元晶体管的阈值分布。

公开(公告)号：US20100149867A1

公开(公告)日：2010-06-17

申请号：US12552671

申请日：2009-09-02

Applicant: Hiroaki Tanaka ,  Hitoshi Shiga

Inventor： Hiroaki Tanaka ,  Hitoshi Shiga

IPC: G11C16/04

CPC classification number: G11C16/0483 ,  G11C16/3418 ,  G11C16/3427

Abstract: A nonvolatile semiconductor memory device includes a nonvolatile memory which includes a block having a plurality of memory cell groups, each of the memory cell groups being electrically connected to a plurality of bit lines and electrically connected to a common word line, each memory cell being recordable of a plurality of bits, a first register which stores information obtained by correcting first data to be written to a first word line, and a control circuit which sets a set potential in the first register and writes the bits to a write target first memory cell at a time using the information in the first register, the set potential being obtained by subtracting, from a target potential to be finally set in the first memory cell, a potential increase which is generated by setting a potential in an unwritten second memory cell adjacent to the first memory cell.

Abstract translation: 非易失性半导体存储器件包括非易失性存储器，其包括具有多个存储单元组的块，每个存储单元组电连接到多个位线并电连接到公共字线，每个存储器单元可记录 多个比特的第一寄存器，存储通过校正要写入第一字线的第一数据而获得的信息的第一寄存器，以及设置第一寄存器中的置位电位并将该位写入写入目标第一存储单元的控制电路 在使用第一寄存器中的信息的同时，通过从第一存储器单元中最终设置的目标电位减去通过将未写入的第二存储单元中的电位设置为相邻而产生的电位增加而获得的设定电位 到第一个存储单元。

公开(公告)号：US07729178B2

公开(公告)日：2010-06-01

申请号：US11849891

申请日：2007-09-04

Applicant: Yasushi Kameda ,  Ken Takeuchi ,  Hitoshi Shiga ,  Takuya Futatsuyama ,  Koichi Kawai

Inventor： Yasushi Kameda ,  Ken Takeuchi ,  Hitoshi Shiga ,  Takuya Futatsuyama ,  Koichi Kawai

IPC: G11C7/10

CPC classification number: G11C16/102

Abstract: The non-volatile semiconductor memory device has a circuit which maintains and holds the potentials of bit lines, and either ones of even-bit lines or odd-bit lines are connected to the circuit. When the bit line potential holding circuit is connected to even-bit lines and a block copy is performed, data is first outputted to the even-bit lines, and after the potential of the even-bit line is determined, the bit line potential holding circuit operates. Then, biasing of the potential of the even-bit lines is carried out by the bit line potential holding circuit, the potentials of the bit lines are maintained and held. At the same time, data is outputted to the odd-bit lines and the potentials of the odd-bit lines are determined. Then, a program voltage is supplied to a selected word line, and data is simultaneously written (programmed) in the memory cells connected to the even-bit lines, and the memory cells connected to the odd-bit lines.

Abstract translation: 非易失性半导体存储器件具有维持并保持位线的电位的电路，偶数位线或奇数位线中的任一个与电路连接。 当位线电位保持电路连接到偶数位线并执行块复制时，首先将数据输出到偶数位线，并且在确定偶数位线的电位之后，位线电位保持 电路工作。 然后，通过位线电位保持电路来执行偶数位线的电位的偏置，保持并保持位线的电位。 同时，将数据输出到奇数位线，并且确定奇数位线的电位。 然后，将编程电压提供给所选择的字线，并且数据被同时写入（编程）到连接到偶数位线的存储器单元中，并且存储器单元连接到奇数位线。

公开(公告)号：US07372744B2

公开(公告)日：2008-05-13

申请号：US11216215

申请日：2005-09-01

Applicant: Hitoshi Shiga ,  Chih-Chung Chen ,  Chih-Hung Wang ,  Sheng-Lin Hung

Inventor： Hitoshi Shiga ,  Chih-Chung Chen ,  Chih-Hung Wang ,  Sheng-Lin Hung

IPC: G11C7/10

CPC classification number: G11C16/102 ,  G11C16/0483 ,  G11C16/26 ,  G11C2207/2236 ,  G11C2216/14

Abstract: A memory system includes a memory cell array, a bit line switch, first and second page buffers, a column switch, an error correction circuit, and control circuits. The second page buffer can swap data with the first page buffer. The control circuits controls the bit line switch and the first and second page buffers, sequentially reads, page by page, one or more pages from the mth (m is a positive integer) page to the nth (n is an integer greater than m) page of the first block in the memory cell array, controls the error correction circuit to perform error correction calculation by the error correction circuit, controls the first and second data buffers and the bit line switch, and controls to perform write in the second block in the erase state in the memory cell array.

Abstract translation: 存储器系统包括存储单元阵列，位线开关，第一和第二页缓冲器，列开关，纠错电路和控制电路。 第二页缓冲区可以与第一页缓冲区交换数据。 控制电路控制位线开关，第一和第二页缓冲器逐页依次读取从第m（m为正整数）页到第n（n为大于m的整数）的一页或多页， 控制误差校正电路进行误差校正电路的误差校正计算，控制第一和第二数据缓冲器和位线开关，并控制在第二块中执行写入 存储单元阵列中的擦除状态。

公开(公告)号：US07161835B2

公开(公告)日：2007-01-09

申请号：US10957826

申请日：2004-10-05

Applicant: Hitoshi Shiga

Inventor： Hitoshi Shiga

IPC: G11C16/06

CPC classification number: G11C16/344 ,  G11C16/0483

Abstract: A semiconductor memory device including: a cell array with electrically rewritable and non-volatile memory cells arranged therein; a sense amplifier circuit configured to read data of and write data into the cell array; and a controller configured to control read, write and erase of the cell array, wherein the controller executes an erase sequence for erasing a selected block in the cell array in response to erase command and address input in such a way of: executing a first erase-verify operation for verifying an erase state of the selected block; ending the erase sequence if the erase state of the selected block has been verified by the first erase-verify operation; whereas executing an erase operation for the selected block if the erase state has not been verified.

Abstract translation: 一种半导体存储器件，包括：具有布置在其中的电可重写和非易失性存储单元的单元阵列; 读出放大器电路，被配置为读取数据并将数据写入单元阵列; 以及控制器，其被配置为控制所述单元阵列的读取，写入和擦除，其中所述控制器响应于擦除命令和地址输入执行用于擦除所述单元阵列中的所选块的擦除序列，其方式为：执行第一擦除 - 验证所选块的擦除状态的操作; 如果所选块的擦除状态已被第一次擦除验证操作验证，则结束擦除序列; 而如果擦除状态尚未被验证，则对所选择的块执行擦除操作。

公开(公告)号：US20060203596A1

公开(公告)日：2006-09-14

申请号：US11193462

申请日：2005-08-01

Applicant: Hitoshi Shiga

Inventor： Hitoshi Shiga

IPC: G11C8/00

CPC classification number: G11C8/12 ,  G11C16/0483 ,  G11C16/08

Abstract: A semiconductor integrated circuit device comprises several blocks including a word line connected with a memory cell, a row decoder selecting the word line, and a block decoder selecting the block. The block decoder includes a logical address register holding logical block address corresponding to the several blocks and a block status register holding a block status. The block decoder selects a block in which input block address and input block status match with held logical block address and held block status, respectively.

Abstract translation: 半导体集成电路器件包括若干块，包括与存储单元连接的字线，选择字线的行解码器和选择该块的块解码器。 块解码器包括保存对应于几个块的逻辑块地址的逻辑地址寄存器和保持块状态的块状态寄存器。 块解码器分别选择输入块地址和输入块状态与保持的逻辑块地址匹配并保持块状态的块。

公开(公告)号：US20060050314A1

公开(公告)日：2006-03-09

申请号：US11216215

申请日：2005-09-01

Applicant: Hitoshi Shiga ,  Chih-Chung Chen ,  Chih-Hung Wang ,  Sheng-Lin Hung

Inventor： Hitoshi Shiga ,  Chih-Chung Chen ,  Chih-Hung Wang ,  Sheng-Lin Hung

IPC: G06K15/00

CPC classification number: G11C16/102 ,  G11C16/0483 ,  G11C16/26 ,  G11C2207/2236 ,  G11C2216/14

Abstract: A memory system includes a memory cell array, a bit line switch, first and second page buffers, a column switch, an error correction circuit, and control circuits. The second page buffer can swap data with the first page buffer. The control circuits controls the bit line switch and the first and second page buffers, sequentially reads, page by page, one or more pages from the mth (m is a positive integer) page to the nth (n is an integer greater than m) page of the first block in the memory cell array, controls the error correction circuit to perform error correction calculation by the error correction circuit, controls the first and second data buffers and the bit line switch, and controls to perform write in the second block in the erase state in the memory cell array.

Abstract translation: 存储器系统包括存储单元阵列，位线开关，第一和第二页缓冲器，列开关，纠错电路和控制电路。 第二页缓冲区可以与第一页缓冲区交换数据。 控制电路控制位线开关，第一和第二页缓冲器逐页依次读取从第m（m为正整数）页到第n（n为大于m的整数）的一页或多页， 控制误差校正电路进行误差校正电路的误差校正计算，控制第一和第二数据缓冲器和位线开关，并控制在第二块中执行写入 存储单元阵列中的擦除状态。

公开(公告)号：US06982904B2

公开(公告)日：2006-01-03

申请号：US10856851

申请日：2004-06-01

Applicant: Hitoshi Shiga

Inventor： Hitoshi Shiga

IPC: G11C16/06

CPC classification number: G11C16/26 ,  G06F11/1068 ,  G11C16/0483 ,  G11C16/3418

Abstract: A non-volatile semiconductor memory device includes: a cell array having electrically rewritable and non-volatile memory cells arranged therein; and a sense amplifier circuit configured to detect voltage change of a bit line in the cell array, thereby reading data of a selected memory cell coupled to the bit line, wherein the sense amplifier circuit is controlled to read data at plural timings within a period in which the bit line voltage is changing in correspondence with the selected memory cell, and compare data read out by successive two data read operations with each other so as to judge a threshold margin of the selected memory cell.

Abstract translation: 非易失性半导体存储器件包括：具有布置在其中的电可重写和非易失性存储单元的单元阵列; 以及读出放大器电路，被配置为检测所述单元阵列中的位线的电压变化，从而读取耦合到所述位线的所选存储单元的数据，其中所述读出放大器电路被控制为在多个定时内在 位线电压与所选择的存储单元相对应地变化，并且通过连续两个数据读取操作读出的数据彼此进行比较，以便判断所选存储单元的阈值余量。

公开(公告)号：US06826068B1

公开(公告)日：2004-11-30

申请号：US10654463

申请日：2003-09-03

Applicant: Hitoshi Shiga ,  Yoshinori Takano ,  Toru Tanzawa ,  Shigeru Atsumi

Inventor： Hitoshi Shiga ,  Yoshinori Takano ,  Toru Tanzawa ,  Shigeru Atsumi

IPC: G11C506

CPC classification number: G11C7/1021 ,  G11C8/10

Abstract: A semiconductor integrated circuit device includes first to fourth bit lines and a redundant bit line, first to fourth column gate transistors and a redundant column gate transistor coupled to each of the first to fourth bit lines and the redundant bit lines, first to fourth column select lines and a redundant column select line coupled to each of the first to fourth column gate transistors and the redundant column gate transistor. The second column select line passes through the first bit line. The third column select line passes through the first and second bit lines. The fourth column select line passes through the first, second and third bit lines. The redundant column select line passes through the first, second, third and fourth bit lines.

Abstract translation: 半导体集成电路器件包括第一至第四位线和冗余位线，第一至第四列栅极晶体管和耦合到第一至第四位线和冗余位线中的每一个的冗余列栅极晶体管，第一至第四列选择 线路以及耦合到第一至第四列栅极晶体管和冗余列栅极晶体管中的每一个的冗余列选择线。 第二列选择线通过第一位线。 第三列选择线通过第一和第二位线。 第四列选择线通过第一，第二和第三位线。 冗余列选择线通过第一，第二，第三和第四位线。

公开(公告)号：US06434054B1

公开(公告)日：2002-08-13

申请号：US10040383

申请日：2002-01-09

Applicant: Hitoshi Shiga ,  Toru Tanzawa ,  Masanobu Saito

Inventor： Hitoshi Shiga ,  Toru Tanzawa ,  Masanobu Saito

IPC: G11C1616

CPC classification number: G11C16/3409 ,  G11C16/16 ,  G11C16/3404 ,  G11C2216/20

Abstract: A non-volatile semiconductor memory device according to the invention comprises a memory cell array having a plurality of non-volatile memory cells, and a write state machine controlling a voltage applied to a memory cell selected from the memory cell array and a voltage application period, in accordance with each of reading of data from the selected memory cell, writing of data into the selected memory cell, and erasion of data from the selected memory. The write state machine executes writing, under a first writing condition, on a predetermined number of memory cells included in the memory cell array, and executes writing on memory cells other than the predetermined number of memory cells, under a second writing condition set in accordance with a result of the writing executed under the first writing condition.

Abstract translation: 根据本发明的非易失性半导体存储器件包括具有多个非易失性存储单元的存储单元阵列，以及控制施加到从存储单元阵列选择的存储单元的电压的写状态机和施加电压的周期 根据从所选择的存储器单元读取数据的每一个，将数据写入所选存储单元，以及从所选存储器中擦除数据。 写入状态机在第一写入条件下执行包含在存储单元阵列中的预定数量的存储单元上的写入，并且在按照相应设置的第二写入条件下执行对除了预定数量的存储单元之外的存储单元的写入 其结果是在第一写入条件下执行写入。