公开(公告)号：US20060172501A1

公开(公告)日：2006-08-03

申请号：US11346107

申请日：2006-02-02

申请人： Tetsuji Ueno ,  Dong-suk Shin ,  Hwa-sung Rhee ,  Ho Lee ,  Seung-hwan Lee

发明人： Tetsuji Ueno ,  Dong-suk Shin ,  Hwa-sung Rhee ,  Ho Lee ,  Seung-hwan Lee

IPC分类号： H01L21/336

CPC分类号： H01L21/26506 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02658 ,  H01L21/02661

摘要： Provided is a method of manufacturing a high-quality silicon epitaxial growth. (SEG) layer on a highly doped silicon substrate. The method includes providing a semiconductor substrate including dopant areas with a predetermined concentration, implanting group IV ions into the substrate, cleaning the substrate using a chlorine-based gas, and forming a silicon epitaxial growth (SEG) layer on the substrate.

摘要翻译： 提供一种制造高质量硅外延生长的方法。 （SEG）层。 该方法包括提供包括具有预定浓度的掺杂剂区域的半导体衬底，将IV族离子注入到衬底中，使用氯基气体清洁衬底，以及在衬底上形成硅外延生长（SEG）层。

公开(公告)号：US07952147B2

公开(公告)日：2011-05-31

申请号：US11802281

申请日：2007-05-22

申请人： Tetsuji Ueno ,  Hwa-sung Rhee ,  Ho Lee

发明人： Tetsuji Ueno ,  Hwa-sung Rhee ,  Ho Lee

IPC分类号： H01L21/70

CPC分类号： H01L27/092 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/7843 ,  H01L29/7848

摘要： A semiconductor device with improved transistor operating and flicker noise characteristics includes a substrate, an analog NMOS transistor and a compressively-strained-channel analog PMOS transistor disposed on the substrate. The device also includes a first etch stop liner (ESL) and a second ESL which respectively cover the NMOS transistor and the PMOS transistor. The relative measurement of flicker noise power of the NMOS and PMOS transistors to flicker noise power of reference unstrained-channel analog NMOS and PMOS transistors at a frequency of 500 Hz is less than 1.

摘要翻译： 具有改善的晶体管操作和闪烁噪声特性的半导体器件包括衬底，模拟NMOS晶体管和设置在衬底上的压缩应变通道模拟PMOS晶体管。 该器件还包括分别覆盖NMOS晶体管和PMOS晶体管的第一蚀刻停止衬垫（ESL）和第二ESL。 在500 Hz频率下，NMOS和PMOS晶体管的闪烁噪声功率相对于参考无约束通道模拟NMOS和PMOS晶体管的闪烁噪声功率的相对测量值小于1。

公开(公告)号：US07714394B2

公开(公告)日：2010-05-11

申请号：US11285978

申请日：2005-11-23

申请人： Dong-Suk Shin ,  Hwa-Sung Rhee ,  Tetsuji Ueno ,  Ho Lee ,  Seung-Hwan Lee

发明人： Dong-Suk Shin ,  Hwa-Sung Rhee ,  Tetsuji Ueno ,  Ho Lee ,  Seung-Hwan Lee

IPC分类号： H01L23/58

CPC分类号： H01L29/7834 ,  H01L21/265 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66628

摘要： A Complementary Metal Oxide Semiconductor (CMOS) device is provided. The CMOS device includes an isolation layer provided in a semiconductor substrate to define first and second active regions. First and second gate patterns are disposed to cross over the first and second active regions, respectively. A first elevated source region and a first elevated drain region are disposed at both sides of the first gate pattern respectively, and a second elevated source region and a second elevated drain region are disposed at both sides of the second gate pattern respectively. The first elevated source/drain regions are provided on the first active region, and the second elevated source/drain regions are provided on the second active region. A first gate spacer is provided between the first gate pattern and the first elevated source/drain regions. A second gate spacer is provided to cover edges of the second elevated source/drain regions adjacent to the second gate pattern and an upper sidewall of the second gate pattern. Methods of fabricating the CMOS device is also provided.

摘要翻译： 提供互补金属氧化物半导体（CMOS）器件。 CMOS器件包括设置在半导体衬底中以限定第一和第二有源区的隔离层。 第一和第二栅极图案分别设置成跨越第一和第二有源区域。 第一升高的源极区域和第一升高的漏极区域分别设置在第一栅极图案的两侧，并且第二升高的源极区域和第二升高的漏极区域分别设置在第二栅极图案的两侧。 第一升高的源极/漏极区域设置在第一有源区上，而第二升高的源极/漏极区域设置在第二有源区域上。 在第一栅极图案和第一升高的源极/漏极区域之间提供第一栅极间隔物。 设置第二栅极间隔物以覆盖与第二栅极图案相邻的第二升高的源极/漏极区域和第二栅极图案的上侧壁的边缘。 还提供了制造CMOS器件的方法。

公开(公告)号：US07611951B2

公开(公告)日：2009-11-03

申请号：US11517246

申请日：2006-09-08

申请人： Tetsuji Ueno ,  Hwa-Sung Rhee ,  Ho Lee

发明人： Tetsuji Ueno ,  Hwa-Sung Rhee ,  Ho Lee

IPC分类号： H01L21/336

CPC分类号： H01L29/7848 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/2658 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66636

摘要： Example embodiments relate to a method of manufacturing a semiconductor device. Other example embodiments relate to a method of manufacturing a metal-oxide-semiconductor (MOS) transistor having an epitaxial region disposed in a lower portion of sidewalls of a gate pattern. Provided is a method of manufacturing a MOS transistor having an epitaxial region which improves an epitaxial growth rate and which may have fewer defects. The method of manufacturing a MOS transistor having an epitaxial region may include forming a gate pattern on a semiconductor substrate, forming a first ion implantation region having a first damage profile by implanting first impurity ions into the semiconductor substrate using the gate pattern as an ion implantation mask, forming a second ion implantation region having a second damage profile adjacent to the first damage profile by implanting second impurity ions into the semiconductor substrate using the gate pattern as an ion implantation mask and partially etching a lower portion of sidewalls of the gate pattern and forming in-situ an epitaxial region on the etched semiconductor substrate.

摘要翻译： 示例实施例涉及制造半导体器件的方法。 其他示例实施例涉及制造具有设置在栅极图案的侧壁的下部中的外延区域的金属氧化物半导体（MOS）晶体管的方法。 提供一种制造具有提高外延生长速率并且可能具有较少缺陷的外延区域的MOS晶体管的方法。 制造具有外延区域的MOS晶体管的方法可以包括在半导体衬底上形成栅极图案，通过使用栅极图案作为离子注入，将第一杂质离子注入到半导体衬底中，形成具有第一损伤分布的第一离子注入区域 通过使用所述栅极图案作为离子注入掩模将所述第二杂质离子注入到所述半导体衬底中，形成具有与所述第一损伤分布相邻的第二损伤分布的第二离子注入区，并部分地蚀刻所述栅极图案的侧壁的下部;以及 在蚀刻的半导体衬底上原位形成外延区域。

公开(公告)号：US07361563B2

公开(公告)日：2008-04-22

申请号：US11299447

申请日：2005-12-09

申请人： Dong-Suk Shin ,  Hwa-Sung Rhee ,  Tetsuji Ueno ,  Ho Lee ,  Seung-Hwan Lee

发明人： Dong-Suk Shin ,  Hwa-Sung Rhee ,  Tetsuji Ueno ,  Ho Lee ,  Seung-Hwan Lee

IPC分类号： H01L21/205 ,  H01L29/80 ,  H01L21/336

CPC分类号： H01L29/7848 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834

摘要： Methods of fabricating a semiconductor device using a selective epitaxial growth technique include forming a recess in a semiconductor substrate. The substrate having the recess is loaded into a reaction chamber. A semiconductor source gas and a main etching gas are injected into the reaction chamber to selectively grow an epitaxial semiconductor layer on a sidewall and on a bottom surface of the recess. A selective etching gas is injected into the reaction chamber to selectively etch a fence of the epitaxial semiconductor layer which is adjacent to the sidewall of the recess and grown to a level that is higher than an upper surface of the semiconductor substrate.

摘要翻译： 使用选择性外延生长技术制造半导体器件的方法包括在半导体衬底中形成凹部。 将具有凹部的基板装入反应室。 将半导体源气体和主蚀刻气体注入到反应室中，以选择性地在凹槽的侧壁和底表面上生长外延半导体层。 选择性蚀刻气体被注入到反应室中，以选择性地蚀刻外延半导体层的与凹槽的侧壁相邻的栅栏，并生长到高于半导体衬底的上表面的水平。

公开(公告)号：US20080067545A1

公开(公告)日：2008-03-20

申请号：US11898978

申请日：2007-09-18

申请人： Hwa-sung Rhee ,  Tetsuji Ueno ,  Ho Lee ,  Myung-sun Kim ,  Ji-hye Yi

发明人： Hwa-sung Rhee ,  Tetsuji Ueno ,  Ho Lee ,  Myung-sun Kim ,  Ji-hye Yi

IPC分类号： H01L29/778 ,  H01L21/336

CPC分类号： H01L21/26513 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

摘要： A semiconductor device having a field effect transistor according to example embodiments may include a first semiconductor pattern disposed to fill a first recess region and a second semiconductor pattern disposed to fill a second recess region. The first recess region may be shallower than the second recess region and may be disposed adjacent to a channel region. Thus, sufficient stress may be supplied to the channel region to increase the mobility of holes or carriers in a channel and enhance a punchthrough characteristic.

摘要翻译： 具有根据示例实施例的场效应晶体管的半导体器件可以包括设置成填充第一凹陷区域的第一半导体图案和设置成填充第二凹陷区域的第二半导体图案。 第一凹部区域可以比第二凹部区域浅，并且可以设置在与沟道区域相邻的位置。 因此，可以向通道区域提供足够的应力以增加通道中的空穴或载流子的迁移率并增强穿透特性。

公开(公告)号：US20050279997A1

公开(公告)日：2005-12-22

申请号：US11154236

申请日：2005-06-16

申请人： Dong-Suk Shin ,  Hwa-Sung Rhee ,  Tetsuji Ueno ,  Ho Lee ,  Seung-Hwan Lee

发明人： Dong-Suk Shin ,  Hwa-Sung Rhee ,  Tetsuji Ueno ,  Ho Lee ,  Seung-Hwan Lee

IPC分类号： H01L21/20 ,  H01L21/205 ,  H01L21/28 ,  H01L21/336 ,  H01L29/772

CPC分类号： H01L21/28044 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636 ,  H01L29/66628 ,  H01L29/66772

摘要： In methods of selectively forming an epitaxial semiconductor layer on a single crystalline semiconductor and semiconductor devices fabricated using the same, a single crystalline epitaxial semiconductor layer and a non-single crystalline epitaxial semiconductor layer are formed on a single crystalline semiconductor and a non-single crystalline semiconductor pattern respectively, using a main semiconductor source gas and a main etching gas. The non-single crystalline epitaxial semiconductor layer is removed using a selective etching gas. The main gases and the selective etching gas are alternately and repeatedly supplied at least two times to selectively form an elevated single crystalline epitaxial semiconductor layer having a desired thickness only on the single crystalline semiconductor. The selective etching gas suppresses formation of an epitaxial semiconductor layer on the non-single crystalline semiconductor pattern.

摘要翻译： 在单晶半导体上选择性地形成外延半导体层的方法和使用其制造的半导体器件的方法中，单晶外延半导体层和非单晶外延半导体层形成在单晶半导体和非单晶 半导体图案，分别使用主半导体源气体和主蚀刻气体。 使用选择性蚀刻气体去除非单晶外延半导体层。 主要气体和选择性蚀刻气体交替地和重复地供应至少两次以选择性地形成仅在单晶半导体上具有期望厚度的升高的单晶外延半导体层。 选择性蚀刻气体抑制在非单晶半导体图案上形成外延半导体层。

公开(公告)号：US08338261B2

公开(公告)日：2012-12-25

申请号：US12851965

申请日：2010-08-06

申请人： Myung-Sun Kim ,  Hwa-Sung Rhee ,  Tetsuji Ueno ,  Ho Lee ,  Ji-Hye Yi

发明人： Myung-Sun Kim ,  Hwa-Sung Rhee ,  Tetsuji Ueno ,  Ho Lee ,  Ji-Hye Yi

IPC分类号： H01L21/336

CPC分类号： H01L29/665 ,  H01L29/165 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： A semiconductor device includes a gate insulator and a gate electrode stacked on a substrate, a source/drain pattern which fills a recess region formed at opposite sides adjacent to the gate electrode, the source/drain pattern being made of silicon-germanium doped with dopants and a metal germanosilicide layer disposed on the source/drain pattern. The metal germanosilicide layer is electrically connected to the source/drain pattern. Moreover, a proportion of germanium amount to the sum of the germanium amount and silicon amount in the metal germanosilicide layer is lower than that of germanium amount to the sum of the germanium amount and silicon amount in the source/drain pattern.

摘要翻译： 半导体器件包括栅极绝缘体和堆叠在衬底上的栅电极，源极/漏极图案填充形成在与栅电极相邻的相对侧的凹陷区域，源极/漏极图案由掺杂有掺杂剂的硅 - 锗构成 和设置在源极/漏极图案上的金属锗硅化物层。 金属锗硅化物层电连接到源极/漏极图案。 此外，与锗源锗排出图案中的锗量和硅量之和的锗量相比，锗量与金锗烷硅化物层中的锗量和硅量之和的比例低。

公开(公告)号：US07619285B2

公开(公告)日：2009-11-17

申请号：US12029884

申请日：2008-02-12

申请人： Dong-suk Shin ,  Hwa-sung Rhee ,  Tetsuji Ueno ,  Ho Lee ,  Seung-hwan Lee

发明人： Dong-suk Shin ,  Hwa-sung Rhee ,  Tetsuji Ueno ,  Ho Lee ,  Seung-hwan Lee

IPC分类号： H01L29/772 ,  H01L21/8238

CPC分类号： H01L29/66636 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/165 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/7848

摘要： A CMOS transistor includes first and second conductivity type MOS transistors. The first conductivity type MOS transistor includes elevated source and drain regions which abut a channel region in a semiconductor substrate and which are formed by elevated epitaxial layers, each including a first epitaxial layer formed in a first recessed of the semiconductor substrate and a second epitaxial layer formed on the first epitaxial layer and extending to a level that is above an upper surface of the semiconductor substrate. The second conductivity type MOS transistor includes recessed source and drain regions which abut a channel region of the semiconductor substrate and which are formed by recessed epitaxial layers, each including a first epitaxial layer formed in a second recess of the semiconductor substrate and a second epitaxial layer formed in the second recess on the first epitaxial layer.

摘要翻译： CMOS晶体管包括第一和第二导电类型的MOS晶体管。 第一导电型MOS晶体管包括升高的源极和漏极区域，其邻接半导体衬底中的沟道区域并且由升高的外延层形成，每个包括形成在半导体衬底的第一凹部中的第一外延层和第二外延层 形成在所述第一外延层上并延伸到所述半导体衬底的上表面之上的水平。 第二导电型MOS晶体管包括凹陷的源极和漏极区域，其邻接半导体衬底的沟道区域并且由凹陷的外延层形成，每个包括形成在半导体衬底的第二凹槽中的第一外延层和第二外延层 形成在第一外延层上的第二凹槽中。

公开(公告)号：US07582535B2

公开(公告)日：2009-09-01

申请号：US11158978

申请日：2005-06-22

申请人： Seung-Hwan Lee ,  Dong-Suk Shin ,  Hwa-Sung Rhee ,  Tetsuji Ueno ,  Ho Lee

发明人： Seung-Hwan Lee ,  Dong-Suk Shin ,  Hwa-Sung Rhee ,  Tetsuji Ueno ,  Ho Lee

IPC分类号： H01L21/336

CPC分类号： H01L29/4975 ,  H01L21/28097 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636

摘要： Methods of fabricating a MOS transistor having a fully silicided metal gate electrode are provided. The method includes forming an isolation layer in a predetermined region of a semiconductor substrate to define an active region. An insulated gate pattern which crosses over the active region is formed. A spacer is formed on sidewalls of the gate pattern. A selective epitaxial growth process is applied to form semiconductor layers on the gate pattern and on the active region at both sides of the gate pattern. In this case, a poly-crystalline semiconductor layer is formed on the gate pattern while single-crystalline semiconductor layers are concurrently formed on the active region at both sides of the gate pattern. The semiconductor layers are selectively etched to form a gate-reduced pattern and elevated source and drain regions. Respective desired thicknesses of the gate-reduced pattern and the elevated source and drain regions may be obtained using an etch selectivity between the poly-crystalline semiconductor layer and the single-crystalline semiconductor layer. A silicidation process is applied to the semiconductor substrate where the gate-reduced pattern is formed to simultaneously form a fully silicided metal gate electrode and elevated source and drain silicide layers.

摘要翻译： 提供制造具有完全硅化金属栅电极的MOS晶体管的方法。 该方法包括在半导体衬底的预定区域中形成隔离层以限定有源区。 形成了跨越有源区域的绝缘栅极图案。 在栅极图案的侧壁上形成间隔物。 施加选择性外延生长工艺以在栅极图案上形成半导体层，并且在栅极图案的两侧形成半导体层。 在这种情况下，在栅极图案上形成多晶半导体层，同时在栅极图案的两侧的有源区同时形成单晶半导体层。 选择性地蚀刻半导体层以形成栅极减小图案和升高的源极和漏极区域。 可以使用多晶半导体层和单晶半导体层之间的蚀刻选择性来获得栅极减小图案和升高的源极和漏极区域的各种期望厚度。 将硅化处理应用于形成栅极减少图案的半导体衬底，以同时形成完全硅化的金属栅电极和升高的源极和漏极硅化物层。