公开(公告)号：US06531896B1

公开(公告)日：2003-03-11

申请号：US09473738

申请日：1999-12-28

Applicant: Hongjiang Song

Inventor： Hongjiang Song

IPC: H03K190175

CPC classification number: H04L25/028 ,  H04L25/0272 ,  H04L25/0282

Abstract: A method includes selecting either a current signaling mode or a voltage signaling mode to communicate with a serial bus. When the current signaling mode is selected, an output stage is placed in the current signaling mode, and when the voltage signaling mode is selected, the output stage is placed in the voltage signaling mode.

Abstract translation: 一种方法包括选择当前信令模式或电压信令模式以与串行总线通信。 当选择当前信令模式时，输出级置于当前信令模式，当选择电压信令模式时，输出级置于电压信令模式。

公开(公告)号：US10164635B2

公开(公告)日：2018-12-25

申请号：US13993675

申请日：2011-12-16

Applicant: Hongjiang Song

Inventor： Hongjiang Song

IPC: H03K19/0175 ,  H04L25/02 ,  G06F1/32

Abstract: Described herein are apparatus, system, and method for improving output signal voltage swing of a voltage mode transmitter (Tx) driver. The Tx driver may use a single power supply which is the same as the power supply of the core processor. The apparatus comprises: a voltage mode driver coupled to an output node; a switching current source, coupled to the output node, to increase voltage swing of a signal on the output node, wherein the signal is driven by the voltage mode driver; and a bias generator to bias the switching current source.

公开(公告)号：US09363070B2

公开(公告)日：2016-06-07

申请号：US13994096

申请日：2011-12-21

Applicant: Hongjiang Song ,  Dianbo Le

Inventor： Hongjiang Song ,  Dianbo Le

IPC: H04L7/00 ,  H03F3/45 ,  H03G1/00 ,  H04L7/10

CPC classification number: H04L7/0079 ,  H03F3/45475 ,  H03F2203/45514 ,  H03F2203/45551 ,  H03G1/0094 ,  H04L7/10

Abstract: Described herein is a low power squelch circuit which comprises a clock generation unit to generate first and second phases of a clock signal; a sampling unit to sample a differential input signal according to the first and second phases of the clock signal, the sampler to generate a sampled differential signal; and a differential amplifier to amplify the sampled differential signal.

Abstract translation: 这里描述的是一种低功率静噪电路，其包括时钟产生单元，用于产生时钟信号的第一和第二相位; 采样单元，用于根据时钟信号的第一和第二相采样差分输入信号，采样器产生采样的差分信号; 以及用于放大采样的差分信号的差分放大器。

公开(公告)号：US20140091851A1

公开(公告)日：2014-04-03

申请号：US13630395

申请日：2012-09-28

Applicant: Hongjiang Song

Inventor： Hongjiang Song

IPC: H03K17/16

CPC classification number: H03K19/0016 ,  G06F1/3287 ,  Y02D10/171

Abstract: In one embodiment, an apparatus includes a power switch to provide a local power voltage at least one gated circuit based on a control signal. The apparatus also includes a delay sensor to provide a delay substantially equivalent to a processing delay of the at least one gated circuit. The apparatus also includes a phase detector to provide the control signal based at least in part on the delay.

Abstract translation: 在一个实施例中，一种装置包括电源开关，用于基于控制信号提供至少一个选通电路的局部电源电压。 该装置还包括延迟传感器，以提供与至少一个选通电路的处理延迟基本上相当的延迟。 该装置还包括相位检测器，用于至少部分地基于延迟来提供控制信号。

公开(公告)号：US07792232B2

公开(公告)日：2010-09-07

申请号：US11170979

申请日：2005-06-30

Applicant: Hongjiang Song

Inventor： Hongjiang Song

IPC: H04L7/00

CPC classification number: H04L7/0025 ,  H04L7/0337

Abstract: A method and apparatus, in some embodiments the apparatus includes a sampler, using a plurality of sampling clocks, to sample a first set of data of an incoming data signal to determine a first phase shift indicator and to sample a second set of data of the incoming data signal to determine a second phase shift indicator, a data recovery circuit (DRC) including control logic to determine a phase control signal based on the first and the second phase shift indicators, and a phase interpolator to receive the phase control signal and adjust a phase of the sampling clocks, wherein the phase interpolator provides the plurality of sampling clocks.

Abstract translation: 一种方法和装置，在一些实施例中，该装置包括采样器，使用多个采样时钟对入射数据信号的第一组数据进行采样，以确定第一相移指示符并对第二组数据采样 输入数据信号以确定第二相移指示符，包括用于基于第一和第二相移指示器确定相位控制信号的控制逻辑的数据恢复电路（DRC）以及用于接收相位控制信号并调整的相位插值器 采样时钟的相位，其中相位内插器提供多个采样时钟。

公开(公告)号：US07653167B2

公开(公告)日：2010-01-26

申请号：US11517162

申请日：2006-09-07

Applicant: Hongjiang Song ,  Tofayel Ahmed

Inventor： Hongjiang Song ,  Tofayel Ahmed

IPC: H04L7/00 ,  H04L25/00 ,  H04L25/40

CPC classification number: H04L7/002 ,  H03L7/0812 ,  H03L7/091

Abstract: Various embodiments provide a Phase Interpolator (PI) that receives input clocks, and outputs intersymbol interference-equalized, phase-shifted output clocks. In one embodiment, the Phase Interpolator comprises two PI Conditioners and a PI Mixer. In one embodiment, a PI Conditioner receives input clocks and is controlled by a different phase-shifted input clock by using a suitable circuit element, such as a flip-flop. Collectively, the input clock-controlled PI Conditioner and Mixer act in concert to control the band limiting effect of the PI Conditioner which, in turn, equalizes intersymbol interference.

Abstract translation: 各种实施例提供接收输入时钟并输出符号间干扰均衡的相移输出时钟的相位插值器（PI）。 在一个实施例中，相位插值器包括两个PI调节器和PI混合器。 在一个实施例中，PI调节器接收输入时钟，并且通过使用诸如触发器的合适电路元件由不同的相移输入时钟控制。 总而言之，输入时钟控制PI调节器和混频器协调一致地控制PI调节器的频带限制效应，这进而使码间干扰相等。

公开(公告)号：US20090074126A1

公开(公告)日：2009-03-19

申请号：US11901782

申请日：2007-09-19

Applicant: Hongjiang Song

Inventor： Hongjiang Song

IPC: H03D3/24

CPC classification number: H04L7/0337 ,  H03L7/07 ,  H03L7/0814 ,  H03L7/091 ,  H04L7/0004 ,  H04L7/0338

Abstract: Embodiments include systems and methods for recovery of data from an incoming digital data stream. Embodiments comprise a fine tracking loop to track the data when the phase between the incoming data and the receiver clock varies relatively slowly. Embodiments comprise a fast tracking loop performs to track the data when the phase between the incoming data and the receiver clock varies rapidly. The fine tracking loop adjusts the phase of a receiver clock to track the data eye of the data. The fast tracking loop over-samples the data and then chooses the sample that best represents the data. In some embodiments, the data recovery circuit can switch between receiving data from the fine tracking loop and receiving data from the fast tracking loop.

Abstract translation: 实施例包括用于从输入数字数据流恢复数据的系统和方法。 实施例包括精细跟踪环路，用于当输入数据和接收机时钟之间的相位相对较慢地变化时跟踪数据。 实施例包括当进入数据和接收机时钟之间的相位迅速变化时，快速跟踪环路执行跟踪数据。 精细跟踪环路调整接收机时钟的相位，以跟踪数据的数据。 快速跟踪循环对数据进行过采样，然后选择最能代表数据的样本。 在一些实施例中，数据恢复电路可以在接收来自精细跟踪环路的数据和从快速跟踪环路接收数据之间切换。

公开(公告)号：US07482857B2

公开(公告)日：2009-01-27

申请号：US10461061

申请日：2003-06-13

Applicant: Hongjiang Song

Inventor： Hongjiang Song

IPC: G05F1/10

CPC classification number: H04B1/0028 ,  H04B1/0007 ,  H04B1/0032 ,  H04B1/28

Abstract: A circuit provides a bandgap reference voltage that is substantially insensitive to temperature variations of an operating reference circuit.

Abstract translation: 电路提供对工作参考电路的温度变化基本上不敏感的带隙基准电压。

公开(公告)号：US20070002989A1

公开(公告)日：2007-01-04

申请号：US11170979

申请日：2005-06-30

Applicant: Hongjiang Song

Inventor： Hongjiang Song

IPC: H04L7/00

CPC classification number: H04L7/0025 ,  H04L7/0337

Abstract: A method and apparatus, in some embodiments the apparatus includes a sampler, using a plurality of sampling clocks, to sample a first set of data of an incoming data signal to determine a first phase shift indicator and to sample a second set of data of the incoming data signal to determine a second phase shift indicator, a data recovery circuit (DRC) including control logic to determine a phase control signal based on the first and the second phase shift indicators, and a phase interpolator to receive the phase control signal and adjust a phase of the sampling clocks, wherein the phase interpolator provides the plurality of sampling clocks.

Abstract translation: 一种方法和装置，在一些实施例中，该装置包括采样器，使用多个采样时钟对入射数据信号的第一组数据进行采样，以确定第一相移指示符并对第二组数据采样 输入数据信号以确定第二相移指示符，包括用于基于第一和第二相移指示器确定相位控制信号的控制逻辑的数据恢复电路（DRC）以及用于接收相位控制信号并调整的相位插值器 采样时钟的相位，其中相位内插器提供多个采样时钟。

公开(公告)号：US20070001775A1

公开(公告)日：2007-01-04

申请号：US11171860

申请日：2005-06-30

Applicant: Hongjiang Song

Inventor： Hongjiang Song

IPC: H03B5/08

CPC classification number: H03B5/1228 ,  H03B5/1215 ,  H03B5/1243 ,  H03B5/1265 ,  H03B2200/0048 ,  H03B2200/005 ,  H03B2201/0208 ,  H03B2201/0266

Abstract: In accordance with certain described implementations, a voltage controlled oscillator (VCO) includes a VCO coarse tuning bank having multiple coarse tuning bank bits. Each coarse tuning bank bit has an associated bit capacitance. The bit capacitances of the coarse tuning bank bits may be selectively engaged using, for example, a single switching transistor for each coarse tuning bank bit.