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    CLOCK REPEATER AND PHASE-ERROR CORRECTING CIRCUIT
    1.
    发明申请
    CLOCK REPEATER AND PHASE-ERROR CORRECTING CIRCUIT 有权
    时钟复位器和相位错误校正电路

    公开(公告)号：US20080144760A1

    公开(公告)日：2008-06-19

    申请号：US11610010

    申请日：2006-12-13

    Applicant: Hongjiang Song ,  Yan Song

    Inventor： Hongjiang Song ,  Yan Song

    IPC: H04L7/00 ,  G06F1/04

    CPC classification number: G06F1/06 ,  H04L7/033

    Abstract: Embodiments of a clock repeater and phase-error correcting circuit are generally described herein. Other embodiments may be described and claimed. In some embodiments, a clock repeater and phase-error correcting circuit may include a polyphase network having a non-symmetrical frequency response selected to reduce static phase error from a multi-phase clock signal, and an output buffer to buffer and to amplify the phase-corrected multi-phase clock signal.

    Abstract translation: 时钟中继器和相位误差校正电路的实施例在此通常被描述。 可以描述和要求保护其他实施例。 在一些实施例中，时钟中继器和相位误差校正电路可以包括具有非对称频率响应的多相网络，其被选择以减少来自多相时钟信号的静态相位误差;以及输出缓冲器，用于缓冲和放大相位 校正的多相时钟信号。

    Switched voltage adaptive slew rate control and spectrum shaping transmitter for high speed digital transmission
    4.
    发明授权
    Switched voltage adaptive slew rate control and spectrum shaping transmitter for high speed digital transmission 失效
    开关电压自适应转换速率控制和频谱整形发射机，用于高速数字传输

    公开(公告)号：US06570931B1

    公开(公告)日：2003-05-27

    申请号：US09476634

    申请日：1999-12-31

    Applicant: Hongjiang Song

    Inventor： Hongjiang Song

    IPC: H04L2704

    CPC classification number: H04L25/03885

    Abstract: An apparatus including a switched voltage bit cell (SVBC) array to receive an input voltage signal, each bit cell of the SVBC array configured to add a voltage to the input voltage signal and a delay locked-loop configured to delay an output voltage signal of each bit cell of the SVBC array by a determined step.

    Abstract translation: 一种装置，包括用于接收输入电压信号的开关电压位单元（SVBC）阵列，所述SVBC阵列的每个比特单元被配置为向所述输入电压信号添加电压，以及延迟锁定环路，被配置为延迟所述输出电压信号的输出电压信号 通过确定的步骤，SVBC阵列的每个位单元。

    Low power digital phase interpolator
    5.
    发明授权
    Low power digital phase interpolator 有权
    低功率数字相位插值器

    公开(公告)号：US08982939B2

    公开(公告)日：2015-03-17

    申请号：US13994627

    申请日：2011-12-21

    Applicant: Hongjiang Song

    Inventor： Hongjiang Song

    IPC: H03H7/30 ,  H04L7/00 ,  H03H11/20 ,  H03H11/22 ,  H03C3/00 ,  H03H17/08 ,  H03K17/693 ,  H03H7/01

    CPC classification number: H04L7/033 ,  H03C3/00 ,  H03C2200/002 ,  H03H11/20 ,  H03H11/22 ,  H03H17/08 ,  H03H2007/0192 ,  H03K17/693 ,  H04L7/0029

    Abstract: Described herein is an apparatus, method and system corresponding to relate to a low power digital phase interpolator (PI). The apparatus comprises: a digital mixer unit to generate phase signals from a series of input signals, the phase signals having phases which are digitally controlled; a poly-phase filter, coupled to the digital mixer unit, to generate a filtered signal by reducing phase error in the phase signals; and an output buffer, coupled to the poly-phase filter, to generate an output signal by buffering the filtered signal. The low power digital PI consumes less power compared to traditional current-mode PIs operating on the same power supply levels because the digital PI is independent of any bias circuit which are needed for current mode PIs.

    Abstract translation: 这里描述了对应于低功率数字相位内插器（PI）的装置，方法和系统。 该装置包括：数字混合器单元，用于从一系列输入信号产生相位信号，相位信号具有数字控制的相位; 耦合到数字混频器单元的多相滤波器，通过减少相位信号中的相位误差来产生滤波信号; 以及耦合到多相滤波器的输出缓冲器，以通过缓冲滤波的信号来产生输出信号。 与传统的电流模式PI相比，低功耗数字PI功耗要低，因为数字PI独立于当前模式PI所需的任何偏置电路。

    LOW VOLTAGE TRANSMITTER WITH VARIABLE OUTPUT SWING
    6.
    发明申请
    LOW VOLTAGE TRANSMITTER WITH VARIABLE OUTPUT SWING 审中-公开
    具有可变输出开关的低电压发射器

    公开(公告)号：US20140055163A1

    公开(公告)日：2014-02-27

    申请号：US13993675

    申请日：2011-12-16

    Applicant: Hongjiang Song

    Inventor： Hongjiang Song

    IPC: H03K19/0175

    CPC classification number: H03K19/017509 ,  G06F1/32 ,  H04L25/0276

    Abstract: Described herein are apparatus, system, and method for improving output signal voltage swing of a voltage mode transmitter (Tx) driver. The Tx driver may use a single power supply which is the same as the power supply of the core processor. The apparatus comprises: a voltage mode driver coupled to an output node; a switching current source, coupled to the output node, to increase voltage swing of a signal on the output node, wherein the signal is driven by the voltage mode driver; and a bias generator to bias the switching current source.

    Abstract translation: 这里描述了用于改善电压模式发射器（Tx）驱动器的输出信号电压摆幅的装置，系统和方法。 Tx驱动器可以使用与核心处理器的电源相同的单个电源。 该装置包括：耦合到输出节点的电压模式驱动器; 耦合到所述输出节点的开关电流源，以增加所述输出节点上的信号的电压摆幅，其中所述信号由所述电压模式驱动器驱动; 以及用于偏置开关电流源的偏置发生器。

    Calibration and testing architecture for receivers
    7.
    发明授权
    Calibration and testing architecture for receivers 有权
    接收机的校准和测试架构

    公开(公告)号：US07409189B2

    公开(公告)日：2008-08-05

    申请号：US10812834

    申请日：2004-03-30

    Applicant: Hongjiang Song

    Inventor： Hongjiang Song

    IPC: H04B17/00

    CPC classification number: H04B17/21

    Abstract: A method and apparatus are provided to generate calibration signals to multiple stages in a receiver channel. The multiple stages are calibrated using multiple calibration circuits, where a controller controls each calibration circuit. The controller is coupled to the output of the final stage in the receiver channel through a single comparison unit. The output from the single comparison unit is used by the controller to calibrate each of the multiple stages.

    Abstract translation: 提供了一种方法和装置，以在接收机通道中的多个级产生校准信号。 多级校准使用多个校准电路，其中控制器控制每个校准电路。 控制器通过单个比较单元耦合到接收机通道中的最后级的输出端。 控制器使用单个比较单元的输出来校准每个多级。

    Locked loop circuit
    8.
    发明授权
    Locked loop circuit 失效
    锁定回路电路

    公开(公告)号：US07324621B2

    公开(公告)日：2008-01-29

    申请号：US09821649

    申请日：2001-03-29

    Applicant: Hongjiang Song

    Inventor： Hongjiang Song

    IPC: H03D3/24

    CPC classification number: H03L7/087 ,  H03L7/0814 ,  H03L7/091

    Abstract: A system includes a locked loop circuit and a processor. The processor is coupled to the locked loop circuit to control the locked loop circuit and perform at least one other function in the system not related to the control of the locked loop circuit.

    Abstract translation: 系统包括锁定环电路和处理器。 处理器耦合到锁定环路电路以控制锁定环路电路并执行与锁定环路电路的控制无关的系统中的至少一个其他功能。

    Converting digital signals to analog signals
    10.
    发明授权
    Converting digital signals to analog signals 有权
    将数字信号转换为模拟信号

    公开(公告)号：US06633248B2

    公开(公告)日：2003-10-14

    申请号：US10226945

    申请日：2002-08-23

    Applicant: Hongjiang Song

    Inventor： Hongjiang Song

    IPC: H03M166

    CPC classification number: H03M1/687 ,  H03M1/0673 ,  H03M1/685 ,  H03M1/747 ,  H03M1/785

    Abstract: A way of converting digital signals to analog signals is provided for wireless communications. An apparatus is provided that comprises a resistive-ladder array to convert a first portion of a digital input signal to a first analog output signal. The apparatus further includes a current-mode array to convert a second portion of the digital input signal to a second analog output signal.

    Abstract translation: 提供了将数字信号转换为模拟信号的方式用于无线通信。 提供了一种装置，其包括电阻梯形阵列，以将数字输入信号的第一部分转换为第一模拟输出信号。 该装置还包括电流模式阵列，用于将数字输入信号的第二部分转换成第二模拟输出信号。

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