公开(公告)号：US20050245064A1

公开(公告)日：2005-11-03

申请号：US10835315

申请日：2004-04-28

申请人： Jung-Chih Tsao ,  Chi-Wen Liu ,  Si-Kua Cheng ,  Che-Tsao Wang ,  Steven Lin ,  Hsien-Ping Feng ,  Chen-Peng Fan

发明人： Jung-Chih Tsao ,  Chi-Wen Liu ,  Si-Kua Cheng ,  Che-Tsao Wang ,  Steven Lin ,  Hsien-Ping Feng ,  Chen-Peng Fan

IPC分类号： H01L21/00 ,  H01L21/4763 ,  H01L21/687 ,  H01L21/768

CPC分类号： H01L21/68728 ,  H01L21/67109 ,  H01L21/68707 ,  H01L21/76877

摘要： A novel method for preventing the formation of voids in metal interconnects fabricated on a wafer, particularly during a thermal anneal process, is disclosed. The method includes fabricating metal interconnects between metal lines on a wafer. During a thermal anneal process carried out to reduce electrical resistance of the interconnects, the wafer is positioned in spaced-apart relationship to a wafer heater. This spacing configuration facilitates enhanced stabilility and uniformity in heating of the wafer by reducing the presence of particles on and providing a uniform flow of heated air or gas against and the wafer backside. This eliminates or at least substantially reduces the formation of voids in the interconnects during the anneal process.

摘要翻译： 公开了一种用于防止在晶片上制造的金属互连中空隙形成的新方法，特别是在热退火工艺期间。 该方法包括在晶片上的金属线之间制造金属互连。 在进行用于降低互连的电阻的热退火工艺期间，晶片以与晶片加热器隔开的关系定位。 这种间隔结构通过减少加热的空气或气体抵靠和晶片背面的颗粒的存在而提高晶片加热的稳定性和均匀性。 这在退火过程中消除或至少基本上减少了互连件中空隙的形成。

公开(公告)号：US07189650B2

公开(公告)日：2007-03-13

申请号：US10987713

申请日：2004-11-12

申请人： Chi-Wen Liu ,  Hsien-Ping Feng ,  Jung-Chih Tsao

发明人： Chi-Wen Liu ,  Hsien-Ping Feng ,  Jung-Chih Tsao

IPC分类号： H01L21/44

CPC分类号： H01L21/76877 ,  C25D3/38 ,  C25D5/10 ,  C25D5/50 ,  C25D7/123 ,  H01L21/2885

摘要： The disclosure relates to a method and apparatus for enhancing copper film quality with a two-step deposition. The two step deposition may include depositing a first copper film by electrochemical plating, annealing the first copper film at a desired temperature for a duration of time to remove any impurities, depositing a second copper film and annealing the second copper film for a duration of time to remove impurities. The second copper film can be deposited by electrochemical plating without HCl/C-based additive. The second copper film can also be deposited by sputtering to avoid impurities including C, Cl and S.

摘要翻译： 本发明涉及一种通过两步沉积来提高铜膜质量的方法和装置。 两级沉积可以包括通过电化学电镀沉积第一铜膜，在所需温度下将第一铜膜退火一段时间以除去任何杂质，沉积第二铜膜并使第二铜膜退火一段时间 去除杂质。 第二个铜膜可以通过不含HCl / C基添加剂的电化学电镀沉积。 也可以通过溅射沉积第二铜膜以避免包括C，Cl和S在内的杂质。

公开(公告)号：US20060105565A1

公开(公告)日：2006-05-18

申请号：US10987713

申请日：2004-11-12

申请人： Chi-Wen Liu ,  Hsien-Ping Feng ,  Jung-Chih Tsao

发明人： Chi-Wen Liu ,  Hsien-Ping Feng ,  Jung-Chih Tsao

IPC分类号： H01L21/4763 ,  H01L21/44

CPC分类号： H01L21/76877 ,  C25D3/38 ,  C25D5/10 ,  C25D5/50 ,  C25D7/123 ,  H01L21/2885

摘要： The disclosure relates to a method and apparatus for enhancing copper film quality with a two-step deposition. The two step deposition may include depositing a first copper film by electrochemical plating, annealing the first copper film at a desired temperature for a duration of time to remove any impurities, depositing a second copper film and annealing the second copper film for a duration of time to remove impurities. The second copper film can be deposited by electrochemical plating without HCl/C-based additive. The second copper film can also be deposited by sputtering to avoid impurities including C, Cl and S.

摘要翻译： 本发明涉及一种通过两步沉积来提高铜膜质量的方法和装置。 两级沉积可以包括通过电化学电镀沉积第一铜膜，在所需温度下将第一铜膜退火一段时间以除去任何杂质，沉积第二铜膜并使第二铜膜退火一段时间 去除杂质。 第二个铜膜可以通过不含HCl / C基添加剂的电化学电镀沉积。 也可以通过溅射沉积第二铜膜以避免包括C，Cl和S在内的杂质。

公开(公告)号：US07183199B2

公开(公告)日：2007-02-27

申请号：US10724201

申请日：2003-12-01

申请人： Chi-Wen Liu ,  Jung-Chih Tsao ,  Shien-Ping Feng ,  Kei-Wei Chen ,  Shih-Chi Lin ,  Ray Chuang

发明人： Chi-Wen Liu ,  Jung-Chih Tsao ,  Shien-Ping Feng ,  Kei-Wei Chen ,  Shih-Chi Lin ,  Ray Chuang

IPC分类号： H01L21/4763

CPC分类号： H01L21/3212 ,  H01L21/7684

摘要： A method of reducing the pattern effect in the CMP process. The method comprises the steps of providing a semiconductor substrate having a patterned dielectric layer, a barrier layer on the patterned dielectric layer, and a conductive layer on the barrier layer; performing a first CMP process to remove part of the conductive layer before the barrier layer is polished, thereby a step height of the conductive layer is reduced; depositing a layer of material substantially the same as the conductive layer on the conductive layer; and performing a second CMP process to expose the dielectric layer. A method of eliminating the dishing phenomena after a CMP process and a CMP rework method are also provided.

摘要翻译： 降低CMP工艺中图案效果的方法。 该方法包括以下步骤：提供具有图案化介电层的半导体衬底，图案化电介质层上的阻挡层和阻挡层上的导电层; 在阻挡层被抛光之前执行第一CMP工艺以去除导电层的一部分，从而降低导电层的台阶高度; 在导电层上沉积与导电层基本相同的材料层; 以及执行第二CMP工艺以暴露所述电介质层。 还提供了在CMP处理和CMP返工方法之后消除凹陷现象的方法。

公开(公告)号：US20050118808A1

公开(公告)日：2005-06-02

申请号：US10724201

申请日：2003-12-01

申请人： Chi-Wen Liu ,  Jung-Chih Tsao ,  Shien-Ping Feng ,  Kei-Wei Chen ,  Shih-Chi Lin ,  Ray Chuang

发明人： Chi-Wen Liu ,  Jung-Chih Tsao ,  Shien-Ping Feng ,  Kei-Wei Chen ,  Shih-Chi Lin ,  Ray Chuang

IPC分类号： H01L21/302 ,  H01L21/321 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/768

CPC分类号： H01L21/3212 ,  H01L21/7684

摘要： A method of reducing the pattern effect in the CMP process. The method comprises the steps of providing a semiconductor substrate having a patterned dielectric layer, a barrier layer on the patterned dielectric layer, and a conductive layer on the barrier layer; performing a first CMP process to remove part of the conductive layer before the barrier layer is polished, thereby a step height of the conductive layer is reduced; depositing a layer of material substantially the same as the conductive layer on the conductive layer; and performing a second CMP process to expose the dielectric layer. A method of eliminating the dishing phenomena after a CMP process and a CMP rework method are also provided.

摘要翻译： 降低CMP工艺中图案效果的方法。 该方法包括以下步骤：提供具有图案化介电层的半导体衬底，图案化电介质层上的阻挡层和阻挡层上的导电层; 在阻挡层被抛光之前执行第一CMP工艺以去除导电层的一部分，从而降低导电层的台阶高度; 在导电层上沉积与导电层基本相同的材料层; 以及执行第二CMP工艺以暴露所述电介质层。 还提供了在CMP处理和CMP返工方法之后消除凹陷现象的方法。

公开(公告)号：US20050121329A1

公开(公告)日：2005-06-09

申请号：US10731331

申请日：2003-12-05

申请人： Jung-Chih Tsao ,  Kei-Wei Chen ,  Chi-Wen Liu ,  Shi-Chi Lin ,  Ray Chuang

发明人： Jung-Chih Tsao ,  Kei-Wei Chen ,  Chi-Wen Liu ,  Shi-Chi Lin ,  Ray Chuang

IPC分类号： C25D5/02 ,  C25D5/06 ,  C25D7/12 ,  C25D17/14 ,  H01L21/288

CPC分类号： H01L21/2885 ,  C25D5/06 ,  C25D17/001 ,  C25D17/14

摘要： A thrust pad assembly which is capable of reducing the quantity of metal electroplated onto the edge region of a substrate to eliminate or reduce the need for edge bevel cleaning or removal of excess metal from the substrate after the electroplating process. The thrust pad assembly includes an air platen through which air is applied at variable pressures to the central and edge regions, respectively, of a thrust pad. The thrust pad applies pressure to a contact ring connected to an electroplating voltage source. The contact ring applies relatively less pressure to the edge region than to the central region of the substrate, thereby reducing the ohmic contact.

摘要翻译： 一种止推垫组件，其能够减少电镀到基板的边缘区域上的金属的量，以消除或减少在电镀工艺之后边缘斜面清洁或从基板上去除多余的金属的需要。 推力垫组件包括空气压板，空气压板分别通过空气压板以可变的压力施加到推力垫的中心和边缘区域。 推力垫对连接到电镀电压源的接触环施加压力。 接触环对边缘区域的压力相对于衬底的中心区域施加相对较小的压力，由此减小欧姆接触。

公开(公告)号：US20050085066A1

公开(公告)日：2005-04-21

申请号：US10687183

申请日：2003-10-16

申请人： Jung-Chih Tsao ,  Chi-Wen Li ,  Kei-Wei Chen ,  Jye-Wei Hsu ,  Hsien-Pin Fong ,  Steven Lin ,  Ray Chuang

发明人： Jung-Chih Tsao ,  Chi-Wen Li ,  Kei-Wei Chen ,  Jye-Wei Hsu ,  Hsien-Pin Fong ,  Steven Lin ,  Ray Chuang

IPC分类号： H01L21/22 ,  H01L21/288 ,  H01L21/38 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/768

CPC分类号： H01L21/76877 ,  H01L21/288 ,  H01L21/7684

摘要： A method of forming a copper interconnect in an opening within a pattern is described. The copper interconnect has an Rs that is nearly independent of opening width and pattern density. A first copper layer having a concave upper surface and thickness t1 is formed in a via or trench in a dielectric layer by depositing copper and performing a first CMP step. A second copper layer with a thickness t2 where t2≦t1 and having a convex lower surface is deposited on the first copper layer by a selective electroplating method. The first and second copper layers are annealed and then a second CMP step planarizes the second copper layer to become coplanar with the dielectric layer. The invention is also a copper interconnect comprised of the aforementioned copper layers where the first copper layer has a grain density (GD1)≧GD2 for the second copper layer.

摘要翻译： 描述了在图案内的开口中形成铜互连的方法。 铜互连具有几乎独立于开口宽度和图案密度的Rs。 通过沉积铜并执行第一CMP步骤，在电介质层中的通孔或沟槽中形成具有凹上表面和厚度t 1的第一铜层。 具有厚度为2 的第二铜层，其中具有凸下表面的第二铜层沉积在第一铜层上 通过选择性电镀方法。 对第一和​​第二铜层进行退火，然后第二CMP步骤将第二铜层平坦化成与电介质层共面。 本发明也是由上述铜层构成的铜布线，其中第一铜层具有第二铜层的晶粒密度（G SUB D1）= G D2 D2。

公开(公告)号：US07208404B2

公开(公告)日：2007-04-24

申请号：US10687183

申请日：2003-10-16

申请人： Jung-Chih Tsao ,  Chi-Wen Li ,  Kei-Wei Chen ,  Jye-Wei Hsu ,  Hsien-Pin Fong ,  Steven Lin ,  Ray Chuang

发明人： Jung-Chih Tsao ,  Chi-Wen Li ,  Kei-Wei Chen ,  Jye-Wei Hsu ,  Hsien-Pin Fong ,  Steven Lin ,  Ray Chuang

IPC分类号： H01L21/4763

CPC分类号： H01L21/76877 ,  H01L21/288 ,  H01L21/7684

摘要： A method of forming a copper interconnect in an opening within a pattern is described. The copper interconnect has an Rs that is nearly independent of opening width and pattern density. A first copper layer having a concave upper surface and thickness t1 is formed in a via or trench in a dielectric layer by depositing copper and performing a first CMP step. A second copper layer with a thickness t2 where t2≦t1 and having a convex lower surface is deposited on the first copper layer by a selective electroplating method. The first and second copper layers are annealed and then a second CMP step planarizes the second copper layer to become coplanar with the dielectric layer. The invention is also a copper interconnect comprised of the aforementioned copper layers where the first copper layer has a grain density (GD1)≧GD2 for the second copper layer.

摘要翻译： 描述了在图案内的开口中形成铜互连的方法。 铜互连具有几乎独立于开口宽度和图案密度的Rs。 通过沉积铜并执行第一CMP步骤，在电介质层中的通孔或沟槽中形成具有凹上表面和厚度t 1的第一铜层。 具有厚度为2 的第二铜层，其中具有凸下表面的第二铜层沉积在第一铜层上 通过选择性电镀方法。 对第一和​​第二铜层进行退火，然后第二CMP步骤将第二铜层平坦化成与电介质层共面。 本发明也是由上述铜层构成的铜布线，其中第一铜层具有第二铜层的晶粒密度（G SUB D1）= G D2 D2。

公开(公告)号：US20050275941A1

公开(公告)日：2005-12-15

申请号：US10854061

申请日：2004-05-26

申请人： Chi-Wen Liu ,  Jung-Chih Tsao ,  Shih-Tzung Chang ,  Ying-Lang Wang ,  Kei-Wei Chen

发明人： Chi-Wen Liu ,  Jung-Chih Tsao ,  Shih-Tzung Chang ,  Ying-Lang Wang ,  Kei-Wei Chen

IPC分类号： G02B23/00 ,  H01L21/768 ,  H01L21/82

CPC分类号： H01L21/7684 ,  H01L21/76877

摘要： A method of forming a metal-filled opening in a semiconductor or other submicron device substrate includes forming a conductive bulk layer over the substrate surface and in the opening, wherein the conductive bulk layer has a first grain size. A conductive cap layer is formed over the conductive bulk layer, the conductive cap layer having a second grain size that is substantially smaller than the first grain size. At least one of the conductive bulk and cap layers are then planarized to form a planar surface that is substantially coincident with the substrate surface.

摘要翻译： 在半导体或其他亚微米器件衬底中形成填充金属的开口的方法包括在衬底表面和开口中形成导电体层，其中导电体层具有第一晶粒尺寸。 导电盖层形成在导电体层之上，导电盖层具有基本上小于第一晶粒尺寸的第二晶粒尺寸。 导电体和盖层中的至少一个然后被平坦化以形成基本上与衬底表面重合的平坦表面。

公开(公告)号：US07252750B2

公开(公告)日：2007-08-07

申请号：US10664347

申请日：2003-09-16

申请人： Chi-Wen Liu ,  Jung-Chih Tsao ,  Ke-Wei Chen ,  Ying-Lang Wang

发明人： Chi-Wen Liu ,  Jung-Chih Tsao ,  Ke-Wei Chen ,  Ying-Lang Wang

IPC分类号： C25D17/00

CPC分类号： C25D5/48 ,  C25D5/028 ,  Y10S204/07

摘要： A dual contact ring for contacting a patterned surface of a wafer and electrochemical plating of a metal on the patterned central region of the wafer and removing the metal from the outer, edge region of the wafer. The dual contact ring has an outer voltage ring in contact with the outer, edge region of the wafer and an inner voltage ring in contact with the inner, central region of the wafer. The outer voltage ring is connected to a positive voltage source and the inner voltage ring is connected to a negative voltage source. The inner voltage ring applies a negative voltage to the wafer to facilitate the plating of metal onto the patterned region of the wafer. A positive voltage is applied to the wafer through the outer voltage ring to remove the plated metal from the outer, edge region of the substrate.

摘要翻译： 用于接触晶片的图案化表面的双接触环和在晶片的图案化中心区域上的金属的电化学电镀，并从晶片的外边缘区域移除金属。 双接触环具有与晶片的外部边缘区域接触的外部电压环和与晶片的内部中心区域接触的内部电压环。 外部电压环连接到正电压源，内部电压环连接到负电压源。 内部电压环向晶片施加负电压以便于将金属电镀到晶片的图案化区域上。 通过外部电压环将正电压施加到晶片，以从衬底的外部边缘区域去除镀覆的金属。