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16 条记录 (耗时 0.054 秒)

    Method for preventing voids in metal interconnects
    1.
    发明申请
    Method for preventing voids in metal interconnects 有权
    防止金属互连中空隙的方法

    公开(公告)号：US20050245064A1

    公开(公告)日：2005-11-03

    申请号：US10835315

    申请日：2004-04-28

    申请人： Jung-Chih Tsao ,  Chi-Wen Liu ,  Si-Kua Cheng ,  Che-Tsao Wang ,  Steven Lin ,  Hsien-Ping Feng ,  Chen-Peng Fan

    发明人： Jung-Chih Tsao ,  Chi-Wen Liu ,  Si-Kua Cheng ,  Che-Tsao Wang ,  Steven Lin ,  Hsien-Ping Feng ,  Chen-Peng Fan

    IPC分类号： H01L21/00 ,  H01L21/4763 ,  H01L21/687 ,  H01L21/768

    CPC分类号： H01L21/68728 ,  H01L21/67109 ,  H01L21/68707 ,  H01L21/76877

    摘要： A novel method for preventing the formation of voids in metal interconnects fabricated on a wafer, particularly during a thermal anneal process, is disclosed. The method includes fabricating metal interconnects between metal lines on a wafer. During a thermal anneal process carried out to reduce electrical resistance of the interconnects, the wafer is positioned in spaced-apart relationship to a wafer heater. This spacing configuration facilitates enhanced stabilility and uniformity in heating of the wafer by reducing the presence of particles on and providing a uniform flow of heated air or gas against and the wafer backside. This eliminates or at least substantially reduces the formation of voids in the interconnects during the anneal process.

    摘要翻译： 公开了一种用于防止在晶片上制造的金属互连中空隙形成的新方法，特别是在热退火工艺期间。 该方法包括在晶片上的金属线之间制造金属互连。 在进行用于降低互连的电阻的热退火工艺期间，晶片以与晶片加热器隔开的关系定位。 这种间隔结构通过减少加热的空气或气体抵靠和晶片背面的颗粒的存在而提高晶片加热的稳定性和均匀性。 这在退火过程中消除或至少基本上减少了互连件中空隙的形成。

    Method for preventing voids in metal interconnects
    2.
    发明授权
    Method for preventing voids in metal interconnects 有权
    防止金属互连中空隙的方法

    公开(公告)号：US07122471B2

    公开(公告)日：2006-10-17

    申请号：US10835315

    申请日：2004-04-28

    申请人： Jung-Chih Tsao ,  Chi-Wen Liu ,  Si-Kua Cheng ,  Che-Tsao Wang ,  Steven Lin ,  Hsien-Ping Feng ,  Chen-Peng Fan

    发明人： Jung-Chih Tsao ,  Chi-Wen Liu ,  Si-Kua Cheng ,  Che-Tsao Wang ,  Steven Lin ,  Hsien-Ping Feng ,  Chen-Peng Fan

    IPC分类号： H01L21/44 ,  H01L21/42 ,  H01L21/268 ,  H01L21/428

    CPC分类号： H01L21/68728 ,  H01L21/67109 ,  H01L21/68707 ,  H01L21/76877

    摘要： A novel method for preventing the formation of voids in metal interconnects fabricated on a wafer, particularly during a thermal anneal process, is disclosed. The method includes fabricating metal interconnects between metal lines on a wafer. During a thermal anneal process carried out to reduce electrical resistance of the interconnects, the wafer is positioned in spaced-apart relationship to a wafer heater. This spacing configuration facilitates enhanced stabilility and uniformity in heating of the wafer by reducing the presence of particles on and providing a uniform flow of heated air or gas against and the wafer backside. This eliminates or at least substantially reduces the formation of voids in the interconnects during the anneal process.

    摘要翻译： 公开了一种用于防止在晶片上制造的金属互连中空隙形成的新方法，特别是在热退火工艺期间。 该方法包括在晶片上的金属线之间制造金属互连。 在进行用于降低互连的电阻的热退火工艺期间，晶片以与晶片加热器隔开的关系定位。 这种间隔结构通过减少加热的空气或气体抵靠和晶片背面的颗粒的存在而提高晶片加热的稳定性和均匀性。 这在退火过程中消除或至少基本上减少了互连件中空隙的形成。

    Method and apparatus for stabilizing plating film impurities
    4.
    发明授权
    Method and apparatus for stabilizing plating film impurities 有权
    用于稳定镀膜杂质的方法和装置

    公开(公告)号：US07481910B2

    公开(公告)日：2009-01-27

    申请号：US10880675

    申请日：2004-06-30

    申请人： Hsien-Ping Feng ,  Ming-Yuang Cheng ,  Si-Kwua Cheng ,  Steven Lin ,  Jung-Chih Tsao ,  Chen-Peng Fan ,  Chi-Wen Liu

    发明人： Hsien-Ping Feng ,  Ming-Yuang Cheng ,  Si-Kwua Cheng ,  Steven Lin ,  Jung-Chih Tsao ,  Chen-Peng Fan ,  Chi-Wen Liu

    IPC分类号： C25D17/00 ,  B01D29/56

    CPC分类号： H01L21/2885 ,  C25D21/06 ,  C25D21/18

    摘要： A method of stabilizing plating film impurities in an electrochemical plating bath solution is disclosed. The method includes providing an electrochemical plating machine in which an electrochemical plating process is carried out. A by-product bath solution is formed by continually removing a pre-filtered bath solution from the machine and removing an additive from the pre-filtered bath solution. A clean bath solution is formed by removing an additive by-product from the by-product bath solution. An additive bath solution is formed by adding a fresh additive to the clean bath solution. The additive bath solution is added to the electrochemical plating machine. An apparatus for stabilizing film impurities in an electrochemical plating bath solution is also disclosed.

    摘要翻译： 公开了一种在电化学镀浴溶液中稳定镀膜杂质的方法。 该方法包括提供其中进行电化学电镀处理的电化学电镀机。 通过从机器中连续除去预过滤的浴液并从预过滤的浴液中除去添加剂形成副产物浴溶液。 通过从副产物浴溶液中除去添加剂副产物形成清洁浴溶液。 通过向清洁浴溶液中加入新鲜添加剂形成添加浴溶液。 将添加浴溶液加入到电化学电镀机中。 还公开了一种用于稳定电化学镀浴溶液中的膜杂质的装置。

    Method for monitoring bubble formation and abnormal via defects in a spin-on-glass planarization, etchback process
    7.
    发明授权
    Method for monitoring bubble formation and abnormal via defects in a spin-on-glass planarization, etchback process 失效
    用于在旋涂玻璃平面化，回蚀工艺中监测气泡形成和异常通孔缺陷的方法

    公开(公告)号：US06248661B1

    公开(公告)日：2001-06-19

    申请号：US09261992

    申请日：1999-03-05

    申请人： Wen-Cheng Chien ,  Chen-Peng Fan

    发明人： Wen-Cheng Chien ,  Chen-Peng Fan

    IPC分类号： H01L214763

    CPC分类号： H01L22/24 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31612 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for monitoring bubble formation in and over a spin-on glass(SOG) layer during the CVD deposition of a superjacent insulative layer is described wherein a monitor wafer is processed either with or without a metal pattern. After a SOG layer has been deposited and cured, a layer of silicon oxide is deposited over it by CVD. If bubbles are formed during the silicon oxide deposition step as a result of out-gassing of the SOG layer, they are entrapped at or near the SOG/silicon oxide interface. The silicon oxide layer is then subjected to a buffered HF etch which exposes the bubbles either by opening them up by eroding the SOG layer underneath the oxide layer or by bringing the surface of the silicon oxide layer closer to the entrapped bubbles, thereby decorating them to make them visible to a white light scanning tool. The monitor wafer is initially scanned just prior to the SOG deposition to obtain a reference scan. A final scan is made after the deposited surface oxide layer has received the buffered HF etch. Bubbles formed over and in an improperly cured SOG layer, occur in clusters that reveal a swirling pattern, reflecting the spin deposition step. The monitor and method of use provides a convenient means for detecting problems with the SOG deposition and curing process, thereby permitting timely remedial action to re-center a deviate process.

    摘要翻译： 描述了在超临界绝缘层的CVD沉积期间监测旋涂玻璃（SOG）层中及其上的气泡形成的方法，其中监测晶片在有或没有金属图案的情况下被处理。 在SOG层沉积和固化之后，通过CVD沉积氧化硅层。 如果在氧化硅沉积步骤期间由于SOG层的排气而形成气泡，则它们被截留在SOG /氧化硅界面处或附近。 然后对氧化硅层进行缓冲的HF蚀刻，其通过将氧化物层下方的SOG层侵蚀或通过使氧化硅层的表面更接近被截留的气泡而打开它们来暴露气泡，由此将其装饰成 使其可见于白光扫描工具。 最初在SOG沉积之前扫描监测晶片，以获得参考扫描。 在沉积的表面氧化物层已经接收缓冲的HF蚀刻之后进行最终扫描。 在不正确固化的SOG层上形成的泡沫发生在显示旋转图案的簇中，反映了旋涂沉积步骤。 显示器和使用方法提供了用于检测SOG沉积和固化过程的问题的便利手段，从而允许及时的补救动作来重新设定偏离过程。

    Nitride spacer technology for flash EPROM
    8.
    发明授权
    Nitride spacer technology for flash EPROM 有权
    闪光EPROM的氮化物间隔技术

    公开(公告)号：US6031264A

    公开(公告)日：2000-02-29

    申请号：US257834

    申请日：1999-02-25

    申请人： Wen-Cheng Chien ,  Hui-Jen Chu ,  Chen-Peng Fan

    发明人： Wen-Cheng Chien ,  Hui-Jen Chu ,  Chen-Peng Fan

    IPC分类号： H01L21/336 ,  H01L29/423 ,  H01L29/788

    CPC分类号： H01L29/66825 ,  H01L29/42324

    摘要： A flash EPROM device includes a floating gate electrode with a top surface and sidewalls is formed on a gate oxide layer covering a semiconductor substrate. A polyoxide cap layer is formed on the top surface of the floating gate electrode. A blanket tunnel oxide layer covers the cap layer, the sidewalls of the floating gate electrode, and the exposed surfaces of the gate oxide layer. A spacer structure is formed on the surface of the tunnel oxide layer adjacent to the sidewalls of the floating gate electrode and above the gate oxide layer. A dielectric, silicon nitride inner spacer, having an annular or an L-shaped cross section, is formed on the blanket tunnel oxide layer adjacent to the sidewalls of the floating gate electrode. In the case of the L-shaped cross section inner spacer, an outer dielectric, spacer is formed over the inner dielectric, spacer. A blanket interelectrode dielectric layer covers the blanket tunnel oxide layer, and the spacer structure. A control gate electrode is formed over the interelectrode dielectric layer on one side of the floating gate electrode.

    摘要翻译： 闪存EPROM器件包括具有顶表面的浮置栅电极，并且在覆盖半导体衬底的栅极氧化物层上形成侧壁。 在浮栅电极的顶表面上形成多孔覆盖层。 覆盖隧道氧化物层覆盖覆盖层，浮栅电极的侧壁和栅极氧化物层的暴露表面。 在与栅极氧化物层的上方相邻的隧道氧化层的表面上形成间隔结构。 具有环形或L形横截面的电介质氮化硅内隔板形成在与浮栅电极的侧壁相邻的橡皮布隧道氧化层上。 在L形横截面内隔片的情况下，在内电介质隔离物上形成外电介质隔离物。 覆盖电极电介质层覆盖覆盖层隧道氧化物层和间隔结构。 在浮栅电极的一侧上的电极间电介质层上形成控制栅电极。

    Nitride spacer technology for flash EPROM
    9.
    发明授权
    Nitride spacer technology for flash EPROM 失效
    闪光EPROM的氮化物间隔技术

    公开(公告)号：US5879993A

    公开(公告)日：1999-03-09

    申请号：US940001

    申请日：1997-09-29

    申请人： Wen-Cheng Chien ,  Hui-Jen Chu ,  Chen-Peng Fan

    发明人： Wen-Cheng Chien ,  Hui-Jen Chu ,  Chen-Peng Fan

    IPC分类号： H01L21/336 ,  H01L29/423 ,  H01L21/8247

    CPC分类号： H01L29/66825 ,  H01L29/42324

    摘要： A method of forming a spacer structure adjacent to the sidewall of a floating gate electrode with a top surface and sidewalls, the floating gate electrode being formed on a silicon oxide dielectric layer, and the silicon oxide dielectric layer being formed on the top surface of a semiconductor substrate include the following steps. Form a cap layer on the floating gate electrode, and a blanket tunnel oxide on the device. Form an inner dielectric, spacer layer over the device including the cap layer and the sidewalls thereby with conforming sidewalls, and an outer dielectric, spacer layer over the inner dielectric, spacer layer including the conforming sidewalls. Partially etch away the outer dielectric, spacer layer with a dry etch to form a outer dielectric spacer adjacent to the conforming sidewalls. Then partially etch away more of the outer dielectric, spacer layer with a wet etch to expose a portion of the conforming sidewalls of the inner dielectric, spacer layer. Finally, etch away the portion of the inner dielectric, spacer layer unprotected by the outer dielectric spacer before forming interelectrode dielectric layers and the control gate electrode.

    摘要翻译： 一种在具有顶表面和侧壁的浮置栅电极的侧壁附近形成间隔结构的方法，所述浮栅电极形成在氧化硅介电层上，所述氧化硅介电层形成在 半导体衬底包括以下步骤。 在浮栅电极上形成覆盖层，在器件上形成覆盖层隧道氧化物。 在该器件上形成内部电介质隔离层，该间隔层包括覆盖层和侧壁，从而具有顺应侧壁，以及位于内部电介质上的外部电介质隔离层，间隔层包括顺应侧壁。 用干蚀刻部分地蚀刻掉外电介质层间隔层，以形成邻近顺应侧壁的外电介质隔离层。 然后用湿蚀刻部分地去除更多的外部电介质隔离层，以暴露内部电介质隔离层的一部分合形侧壁。 最后，在形成电极间电介质层和控制栅极电极之前，蚀刻外部电介质间隔物未被保护的内部电介质隔离层的部分。

    Solution for copper hillock induced by thermal strain with buffer zone for strain relaxation
    10.
    发明授权
    Solution for copper hillock induced by thermal strain with buffer zone for strain relaxation 有权
    用于应变松弛的缓冲区的热应变诱导的铜小丘的解决方案

    公开(公告)号：US06897147B1

    公开(公告)日：2005-05-24

    申请号：US10758315

    申请日：2004-01-15

    申请人： Shin-Yeu Tsai ,  Po-Hsiung Leu ,  Chia-Ming Yang ,  Tsang-Yu Liu ,  Yun-Da Fan ,  Chen-Peng Fan

    发明人： Shin-Yeu Tsai ,  Po-Hsiung Leu ,  Chia-Ming Yang ,  Tsang-Yu Liu ,  Yun-Da Fan ,  Chen-Peng Fan

    IPC分类号： H01L21/28 ,  H01L21/3205 ,  H01L21/44 ,  H01L21/768

    CPC分类号： H01L21/76838

    摘要： A method of reducing copper hillocks in copper metallization is described. An opening is made through a dielectric layer overlying a substrate on a wafer. A copper layer is formed overlying the dielectric layer and completely filling the opening. The copper layer is polished back to leave the copper layer only within the opening. Copper hillocks are reduced by applying F ions to the copper layer to form a buffer zone on a surface of the copper layer and in-situ depositing a capping layer overlying the copper layer. The F ions remove copper oxide naturally formed on the copper surface and the buffer zone transfers thermal vertical strain in the copper to horizontal strain thereby preventing formation of copper hillocks.

    摘要翻译： 描述了一种在铜金属化中减少铜小丘的方法。 通过覆盖晶片上的衬底的电介质层形成开口。 形成覆盖在电介质层上并完全填充开口的铜层。 铜层被抛光回去，仅在开口内留下铜层。 通过将铜离子施加到铜层以在铜层的表面上形成缓冲区并原位沉积覆盖铜层的覆盖层来减少铜小丘。 F离子去除在铜表面上自然形成的氧化铜，缓冲区将铜中的热垂直应变转移到水平应变，从而防止形成铜海丘。