公开(公告)号：US10419016B2

公开(公告)日：2019-09-17

申请号：US15972827

申请日：2018-05-07

Applicant: Huawei Technologies Co., Ltd.

Inventor： Jinda Yang ,  Liren Zhou

IPC: H03M1/12 ,  H03M1/66 ,  H03M1/74 ,  G10L15/12 ,  H03M1/38 ,  H03M1/42 ,  H03M1/76 ,  G06F1/10 ,  H03M1/08

Abstract: An ADC and an analog-to-digital conversion method are provided. The ADC includes: a clock generator, including M transmission gates, where the M transmission gates are configured to receive a first clock signal that is periodically sent and separately perform gating control on the first clock signal, so as to generate M second clock signals, M is an integer that is greater than or equal to 2; M ADC channels that are configured in a time interleaving manner, configured to receive one analog signal and separately perform, under the control of the M second clock signals, sampling and analog-to-digital conversion on the analog signal, so as to obtain M digital signals, where each ADC channel is corresponding to one clock signal of the M second clock signals; and an adder, configured to add the M digital signals together in a digital field, so as to obtain a digital output signal.

公开(公告)号：US20180076804A1

公开(公告)日：2018-03-15

申请号：US15700916

申请日：2017-09-11

Applicant: Huawei Technologies Co., Ltd.

Inventor： Jinda Yang ,  Liren Zhou

IPC: H03K5/15

CPC classification number: H03K5/1508 ,  H03K2005/00286

Abstract: A multi-channel clock distribution circuit and an electronic device includes a power source, a first switch, and at least two clock distribution sub-circuits; each clock distribution sub-circuit includes a second switch, a third switch, and a capacitor; a first end of the capacitor is connected to the power source by using the second switch and is connected to the first end of the first switch by using the third switch, a second end of the capacitor is grounded, and the first end of the capacitor is used as an output end of the clock distribution sub-circuits; and connection and disconnection of the first switch is controlled by a first clock signal, connection and disconnection of the second switch is controlled by a second clock signal, and connection and disconnection of the third switch is controlled by a third clock signal.

公开(公告)号：US20170310336A1

公开(公告)日：2017-10-26

申请号：US15633474

申请日：2017-06-26

Applicant: Huawei Technologies Co., Ltd.

Inventor： Jinda Yang ,  Liren Zhou

IPC: H03M1/74 ,  H03M1/38 ,  G10L15/12 ,  H03M1/12 ,  H03M1/76 ,  H03M1/42

CPC classification number: H03M1/747 ,  G06F1/10 ,  G10L15/12 ,  H03M1/0836 ,  H03M1/1205 ,  H03M1/1215 ,  H03M1/38 ,  H03M1/42 ,  H03M1/76

Abstract: Present invention discloses an ADC and an analog-to-digital conversion method. The ADC includes: a clock generator, including M transmission gates, where the M transmission gates are configured to receive a first clock signal that is periodically sent and separately perform gating control on the first clock signal, so as to generate M second clock signals, M is an integer that is greater than or equal to 2; M ADC channels that are configured in a time interleaving manner, configured to receive one analog signal and separately perform, under the control of the M second clock signals, sampling and analog-to-digital conversion on the analog signal, so as to obtain M digital signals, where each ADC channel is corresponding to one clock signal of the M second clock signals; and an adder, configured to add the M digital signals together in a digital field, so as to obtain a digital output signal.

公开(公告)号：US20150102952A1

公开(公告)日：2015-04-16

申请号：US14509806

申请日：2014-10-08

Applicant: Huawei Technologies Co., Ltd.

Inventor： Jinda Yang ,  Liren Zhou ,  Jun Xiong

IPC: H03M1/38 ,  H03K3/012 ,  H03K17/693 ,  H03M1/00 ,  H03M1/06 ,  H03M1/12 ,  H03K3/037 ,  H03K3/013

CPC classification number: H03K17/693 ,  H03K3/012 ,  H03K3/013 ,  H03K3/037 ,  H03K5/2481 ,  H03M1/0617 ,  H03M1/124 ,  H03M1/164

Abstract: Embodiments of the present invention provide a comparator and an analog-to-digital converter. A sampling module, a pre-amplifying module, and a coupling module in the comparator obtain a third differential voltage signal according to a positive input signal and a negative reference signal, and obtain a fourth differential voltage signal according to a negative input signal and a positive reference signal. A latch that is in the comparator and formed by a first P-type field effect transistor, a second P-type field effect transistor, a third field effect transistor, a fourth field effect transistor, a first switch, and a second switch is directly cross-coupled through gates, and directly collects the third differential voltage signal and the fourth differential voltage signal to the gates, so as to drive the latch to start positive feedback.

Abstract translation: 本发明的实施例提供一种比较器和模数转换器。 比较器中的采样模块，预放大模块和耦合模块根据正输入信号和负参考信号获得第三差分电压信号，并根据负输入信号和 正参考信号。 在比较器中由第一P型场效应晶体管，第二P型场效应晶体管，第三场效应晶体管，第四场效应晶体管，第一开关和第二开关形成的锁存器直接 通过栅极交叉耦合，并将第三差分电压信号和第四差分电压信号直接收集到门，以驱动锁存器启动正反馈。