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公开(公告)号：US10804922B2
公开(公告)日：2020-10-13
申请号：US16434593
申请日：2019-06-07
Applicant: Huawei Technologies Co., Ltd.
Inventor： Jinda Yang , Liren Zhou
IPC: H03M3/00 , H03K3/00 , H03M1/46 , G06F1/06 , H03L7/183 , H03M1/06 , H03M1/10 , H03M1/12 , G06F1/10
Abstract: A sampling clock generating circuit and an analog to digital converter (ADC) includes a variable resistance circuit, a NOT-gate type circuit, and a capacitor, where an input end of the NOT-gate type circuit receives a pulse signal whose period is T, an output end of the NOT-gate type circuit is coupled to one end of the capacitor, the other end of the capacitor is grounded, a power supply terminal of the NOT-gate type circuit is connected to a power supply, a ground terminal of the NOT-gate type circuit is coupled to one end of the variable resistance circuit, and the other end of the variable resistance circuit is grounded, the NOT-gate type circuit is configured to output a low level when the pulse signal is a high level, and output a high level when the pulse signal is a low level.
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公开(公告)号：US09991902B2
公开(公告)日：2018-06-05
申请号：US15633474
申请日：2017-06-26
Applicant: Huawei Technologies Co., Ltd.
Inventor： Jinda Yang , Liren Zhou
CPC classification number: H03M1/747 , G06F1/10 , G10L15/12 , H03M1/0836 , H03M1/1205 , H03M1/1215 , H03M1/38 , H03M1/42 , H03M1/76
Abstract: An ADC and an analog-to-digital conversion method are provided. The ADC includes: a clock generator, including M transmission gates, where the M transmission gates are configured to receive a first clock signal that is periodically sent and separately perform gating control on the first clock signal, so as to generate M second clock signals, M is an integer that is greater than or equal to 2; M ADC channels that are configured in a time interleaving manner, configured to receive one analog signal and separately perform, under the control of the M second clock signals, sampling and analog-to-digital conversion on the analog signal, so as to obtain M digital signals, where each ADC channel is corresponding to one clock signal of the M second clock signals; and an adder, configured to add the M digital signals together in a digital field, so as to obtain a digital output signal.
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公开(公告)号：US10122354B2
公开(公告)日：2018-11-06
申请号：US15700916
申请日：2017-09-11
Applicant: Huawei Technologies Co., Ltd.
Inventor： Jinda Yang , Liren Zhou
Abstract: A multi-channel clock distribution circuit and an electronic device includes a power source, a first switch, and at least two clock distribution sub-circuits; each clock distribution sub-circuit includes a second switch, a third switch, and a capacitor; a first end of the capacitor is connected to the power source by using the second switch and is connected to the first end of the first switch by using the third switch, a second end of the capacitor is grounded, and the first end of the capacitor is used as an output end of the clock distribution sub-circuits; and connection and disconnection of the first switch is controlled by a first clock signal, connection and disconnection of the second switch is controlled by a second clock signal, and connection and disconnection of the third switch is controlled by a third clock signal.
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公开(公告)号：US20190363726A1
公开(公告)日：2019-11-28
申请号：US16434593
申请日：2019-06-07
Applicant: Huawei Technologies Co., Ltd.
Inventor： Jinda Yang , Liren Zhou
Abstract: A sampling clock generating circuit and an analog to digital converter (ADC) includes a resistance variable circuit, a NOT-gate type circuit, and a capacitor, where an input end of the NOT-gate type circuit receives a pulse signal whose period is T, an output end of the NOT-gate type circuit is coupled to one end of the capacitor, the other end of the capacitor is grounded, a power supply terminal of the NOT-gate type circuit is connected to a power supply, a ground terminal of the NOT-gate type circuit is coupled to one end of the resistance variable circuit, and the other end of the resistance variable circuit is grounded, the NOT-gate type circuit is configured to output a low level when the pulse signal is a high level, and output a high level when the pulse signal is a low level.
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公开(公告)号：US20150303919A1
公开(公告)日：2015-10-22
申请号：US14672919
申请日：2015-03-30
Applicant: Huawei Technologies Co., Ltd.
Inventor： Liren Zhou , Jun Xiong
IPC: H03K19/0185 , H03M1/66
CPC classification number: H03K19/0185 , H03M1/66
Abstract: Provided are a level shifter and a digital to analog converter, which can make a minimum value of an output voltage be greater than 0. In the circuit, sources of a first field effect transistor and a second field effect transistor are connected to a first direct current power supply; a drain of the first field effect transistor and a gate of the second field effect transistor are connected to one terminal of a first capacitor; a connecting end formed after the other terminal of the first capacitor is connected to an input end of a phase inverter is used as a digital signal input end; a gate of the first field effect transistor, a drain of the second field effect transistor, a source of a third field effect transistor, and a source of a fifth field effect transistor are connected to one terminal of a second capacitor.
Abstract translation: 提供了一种电平移位器和数模转换器，其可以使输出电压的最小值大于0.在电路中，第一场效应晶体管和第二场效应晶体管的源极连接到第一直接 当前电源; 第一场效应晶体管的漏极和第二场效应晶体管的栅极连接到第一电容器的一个端子; 在第一电容器的另一个端子连接到相位逆变器的输入端之后形成的连接端被用作数字信号输入端; 第一场效应晶体管的栅极，第二场效应晶体管的漏极，第三场效应晶体管的源极和第五场效应晶体管的源极连接到第二电容器的一个端子。
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Patent Agency Ranking
公开(公告)号：US09035680B2
公开(公告)日：2015-05-19
申请号：US14509806
申请日：2014-10-08
Applicant: Huawei Technologies Co., Ltd.
Inventor： Jinda Yang , Liren Zhou , Jun Xiong
IPC: H03K5/22 , H03M1/38 , H03K3/037 , H03K3/012 , H03K3/013 , H03M1/00 , H03M1/06 , H03M1/12 , H03K17/693
CPC classification number: H03K17/693 , H03K3/012 , H03K3/013 , H03K3/037 , H03K5/2481 , H03M1/0617 , H03M1/124 , H03M1/164
Abstract: Embodiments of the present invention provide a comparator and an analog-to-digital converter. A sampling module, a pre-amplifying module, and a coupling module in the comparator obtain a third differential voltage signal according to a positive input signal and a negative reference signal, and obtain a fourth differential voltage signal according to a negative input signal and a positive reference signal. A latch that is in the comparator and formed by a first P-type field effect transistor, a second P-type field effect transistor, a third field effect transistor, a fourth field effect transistor, a first switch, and a second switch is directly cross-coupled through gates, and directly collects the third differential voltage signal and the fourth differential voltage signal to the gates, so as to drive the latch to start positive feedback.
Abstract translation: 本发明的实施例提供一种比较器和模数转换器。 比较器中的采样模块，预放大模块和耦合模块根据正输入信号和负参考信号获得第三差分电压信号，并根据负输入信号和 正参考信号。 在比较器中由第一P型场效应晶体管，第二P型场效应晶体管，第三场效应晶体管，第四场效应晶体管，第一开关和第二开关形成的锁存器直接 通过栅极交叉耦合，并将第三差分电压信号和第四差分电压信号直接收集到门，以驱动锁存器启动正反馈。
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公开(公告)号：US10320409B2
公开(公告)日：2019-06-11
申请号：US15699723
申请日：2017-09-08
Applicant: Huawei Technologies Co., Ltd.
Inventor： Jinda Yang , Liren Zhou
Abstract: A sampling clock generating circuit and an analog to digital converter includes a variable resistance circuit, and a NOT-gate type circuit, where an input end of the NOT-gate type circuit receives a pulse signal whose period is T; a power supply terminal of the NOT-gate type circuit is connected to a power supply; a ground terminal of the NOT-gate type circuit is connected to one end of the variable resistance circuit; and the other end of the variable resistance circuit is grounded; the NOT-gate type circuit is configured to: when the pulse signal is a high level, output a low level; and when the pulse signal is a low level, output a high level.
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公开(公告)号：US09577617B2
公开(公告)日：2017-02-21
申请号：US15167127
申请日：2016-05-27
Applicant: Huawei Technologies Co., Ltd.
Inventor： Jinda Yang , Liren Zhou
IPC: H03L5/00 , H03K3/356 , H03K19/0185 , H03K3/012
CPC classification number: H03K3/356104 , H03K3/012 , H03K19/018521
Abstract: The present invention provides a level conversion circuit. The circuit is as follows: A cathode of a first equivalent diode is connected to a reference voltage, and an anode of the first equivalent diode is separately connected to a gate of a first switching transistor and a first end of a first capacitor; a second end of the first switching transistor and a first end of a second switching transistor are connected together; a second end of the second capacitor is separately connected to a cathode of a second equivalent diode and a gate of the second switching transistor; and a second end of the second switching transistor is grounded, and an anode of the second equivalent diode is connected to a reference voltage.
Abstract translation: 本发明提供一种电平转换电路。 电路如下：第一等效二极管的阴极连接到参考电压，第一等效二极管的阳极分别连接到第一开关晶体管的栅极和第一电容器的第一端; 第一开关晶体管的第二端和第二开关晶体管的第一端连接在一起; 第二电容器的第二端分别连接到第二等效二极管的阴极和第二开关晶体管的栅极; 并且第二开关晶体管的第二端接地，并且第二等效二极管的阳极连接到参考电压。
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公开(公告)号：US20160352312A1
公开(公告)日：2016-12-01
申请号：US15167127
申请日：2016-05-27
Applicant: Huawei Technologies Co., Ltd.
Inventor： Jinda Yang , Liren Zhou
IPC: H03K3/356 , H03K3/012 , H03K19/0185
CPC classification number: H03K3/356104 , H03K3/012 , H03K19/018521
Abstract: The present invention provides a level conversion circuit. The circuit is as follows: A cathode of a first equivalent diode is connected to a reference voltage, and an anode of the first equivalent diode is separately connected to a gate of a first switching transistor and a first end of a first capacitor; a second end of the first switching transistor and a first end of a second switching transistor are connected together; a second end of the second capacitor is separately connected to a cathode of a second equivalent diode and a gate of the second switching transistor; and a second end of the second switching transistor is grounded, and an anode of the second equivalent diode is connected to a reference voltage.
Abstract translation: 本发明提供一种电平转换电路。 电路如下：第一等效二极管的阴极连接到参考电压，第一等效二极管的阳极分别连接到第一开关晶体管的栅极和第一电容器的第一端; 第一开关晶体管的第二端和第二开关晶体管的第一端连接在一起; 第二电容器的第二端分别连接到第二等效二极管的阴极和第二开关晶体管的栅极; 并且第二开关晶体管的第二端接地，并且第二等效二极管的阳极连接到参考电压。
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公开(公告)号：US09172375B1
公开(公告)日：2015-10-27
申请号：US14672919
申请日：2015-03-30
Applicant: Huawei Technologies Co., Ltd.
Inventor： Liren Zhou , Jun Xiong
IPC: H03M1/00 , H03K19/0185 , H03M1/66
CPC classification number: H03K19/0185 , H03M1/66
Abstract: Provided are a level shifter and a digital to analog converter, which can make a minimum value of an output voltage be greater than 0. In the circuit, sources of a first field effect transistor and a second field effect transistor are connected to a first direct current power supply; a drain of the first field effect transistor and a gate of the second field effect transistor are connected to one terminal of a first capacitor; a connecting end formed after the other terminal of the first capacitor is connected to an input end of a phase inverter is used as a digital signal input end; a gate of the first field effect transistor, a drain of the second field effect transistor, a source of a third field effect transistor, and a source of a fifth field effect transistor are connected to one terminal of a second capacitor.
Abstract translation: 提供了一种电平移位器和数模转换器，其可以使输出电压的最小值大于0.在电路中，第一场效应晶体管和第二场效应晶体管的源极连接到第一直接 当前电源; 第一场效应晶体管的漏极和第二场效应晶体管的栅极连接到第一电容器的一个端子; 在第一电容器的另一个端子连接到相位逆变器的输入端之后形成的连接端被用作数字信号输入端; 第一场效应晶体管的栅极，第二场效应晶体管的漏极，第三场效应晶体管的源极和第五场效应晶体管的源极连接到第二电容器的一个端子。
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