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    Methods of forming contact structures and semiconductor devices fabricated using contact structures
    11.
    发明授权
    Methods of forming contact structures and semiconductor devices fabricated using contact structures 有权
    形成接触结构的方法和使用接触结构制造的半导体器件

    公开(公告)号：US08021977B2

    公开(公告)日：2011-09-20

    申请号：US12627810

    申请日：2009-11-30

    申请人： Young-Lim Park ,  Hyeong-Geun An ,  Gyu-Hwan Oh ,  Dong-Ho Ahn ,  Jin-Il Lee

    发明人： Young-Lim Park ,  Hyeong-Geun An ,  Gyu-Hwan Oh ,  Dong-Ho Ahn ,  Jin-Il Lee

    IPC分类号： H01L21/4763 ,  H01L21/768

    CPC分类号： H01L21/76816 ,  H01L27/24

    摘要： Provided are methods of forming contact structures and semiconductor devices fabricated using the contact structures. The formation of a contact structure can include forming a first molding pattern on a substrate, forming an insulating layer to cover at least a sidewall of the first molding pattern, forming a second molding pattern to cover a sidewall of the insulating layer and spaced apart from the first molding pattern, removing a portion of the insulating layer between the first and second molding patterns to form a hole, and forming an insulating pattern between the first and second molding patterns, and forming a contact pattern in the hole.

    摘要翻译： 提供了形成使用接触结构制造的接触结构和半导体器件的方法。 接触结构的形成可以包括在基底上形成第一模制图案，形成绝缘层以覆盖至少第一模制图案的侧壁，形成第二模制图案以覆盖绝缘层的侧壁并与 第一模制图案，去除第一和第二模制图案之间的绝缘层的一部分以形成孔，并且在第一和第二模制图案之间形成绝缘图案，并在孔中形成接触图案。

    Methods of forming multi-level cell of semiconductor memory
    12.
    发明申请
    Methods of forming multi-level cell of semiconductor memory 有权
    形成半导体存储器多级单元的方法

    公开(公告)号：US20100093130A1

    公开(公告)日：2010-04-15

    申请号：US12587772

    申请日：2009-10-13

    申请人： Gyu-Hwan Oh ,  Hyeong-Geun An ,  Soon-Oh Park ,  Dong-Ho Ahn ,  Young-Lim Park

    发明人： Gyu-Hwan Oh ,  Hyeong-Geun An ,  Soon-Oh Park ,  Dong-Ho Ahn ,  Young-Lim Park

    IPC分类号： H01L21/06

    CPC分类号： H01L45/141 ,  H01L27/2409 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/144 ,  H01L45/1666 ,  H01L45/1683

    摘要： Provided is a method of forming a semiconductor memory cell in which in order to store two bits or more data in a memory cell, three or more bottom electrode contacts (BECs) and phase-change materials (GST) have a parallel structure on a single contact plug (CP) and set resistances are changed depending on thicknesses (S), lengths (L) or resistivities (ρ) of the three or more bottom electrode contacts, so that a reset resistance and three different set resistances enable data other than in set and reset states to be stored. Also, a method of forming a memory cell in which three or more phase-change materials (GST) have a parallel structure on a single bottom electrode contact, and the phase-change materials have different set resistances depending on composition ratio or type, so that four or more different resistances can be implemented is provided.

    摘要翻译： 提供了一种形成半导体存储单元的方法，其中为了在存储单元中存储两个或更多个数据，三个或更多个底部电极触点（BEC）和相变材料（GST）在单个存储单元上具有并联结构 接触插头（CP）和设定电阻根据三个或更多个底部电极触点的厚度（S），长度（L）或电阻率（＆rgr）而改变，因此复位电阻和三种不同的设定电阻使数据不能 在设置和复位状态下存储。 此外，形成其中三个或更多个相变材料（GST）在单个底部电极接触上具有平行结构的存储单元的方法，并且相变材料根据组成比或类型具有不同的设定电阻，因此 可以实现四个或更多个不同的电阻。

    Phase changeable memory cell array region and method of forming the same
    16.
    发明授权
    Phase changeable memory cell array region and method of forming the same 有权
    相变存储单元阵列区域及其形成方法

    公开(公告)号：US07638787B2

    公开(公告)日：2009-12-29

    申请号：US11581012

    申请日：2006-10-16

    申请人： Hyeong-Geun An ,  Hideki Horii ,  Sang-Yeol Kang

    发明人： Hyeong-Geun An ,  Hideki Horii ,  Sang-Yeol Kang

    IPC分类号： H01L29/02 ,  G11C11/00

    CPC分类号： H01L45/144 ,  H01L27/2436 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1293 ,  H01L45/165 ,  H01L45/1666

    摘要： A phase changeable memory cell array region includes a lower interlayer insulating layer disposed on a semiconductor substrate. The region also includes a plurality of conductive plugs disposed through the lower interlayer insulating layer. The region also includes a phase changeable material pattern operably disposed on the lower interlayer insulating layer, the phase changeable pattern covering at least two of the plurality of conductive plugs, wherein the phase changeable material pattern includes a plurality of first regions in contact with one or more of the plurality of conductive plugs and at least one second region interposed between the plurality of the first regions, wherein the at least one second region has a lower thermal conductivity than the plurality of first regions. The phase changeable memory cell array region also includes an upper interlayer insulating layer covering at least one of the phase changeable material pattern and the lower interlayer insulating layer. The region also includes conductive patterns disposed through the upper interlayer insulating layer and electrically connected to a plurality of predetermined regions of the plurality of first regions.

    摘要翻译： 相变存储单元阵列区域包括设置在半导体衬底上的下层间绝缘层。 该区域还包括穿过下层间绝缘层设置的多个导电插塞。 所述区域还包括可操作地设置在所述下层间绝缘层上的可相变材料图案，所述相变图案覆盖所述多个导电插塞中的至少两个，其中所述相变材料图案包括多个与第 多个导电插塞中的多个和插入在多个第一区域之间的至少一个第二区域，其中至少一个第二区域具有比多个第一区域更低的热导率。 相变存储单元阵列区域还包括覆盖相变材料图案和下层间绝缘层中的至少一个的上层间绝缘层。 该区域还包括通过上层间绝缘层设置并电连接到多个第一区域中的多个预定区域的导电图案。

    PHASE CHANGEABLE MEMORY CELL ARRAY REGION AND METHOD OF FORMING THE SAME
    17.
    发明申请
    PHASE CHANGEABLE MEMORY CELL ARRAY REGION AND METHOD OF FORMING THE SAME 有权
    相变记忆体区域及其形成方法

    公开(公告)号：US20100055831A1

    公开(公告)日：2010-03-04

    申请号：US12617782

    申请日：2009-11-13

    申请人： Hyeong-Geun An ,  Hideki Horii ,  Sang-Yeol Kang

    发明人： Hyeong-Geun An ,  Hideki Horii ,  Sang-Yeol Kang

    IPC分类号： H01L21/06

    CPC分类号： H01L45/144 ,  H01L27/2436 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1293 ,  H01L45/165 ,  H01L45/1666

    摘要： A phase changeable memory cell array region includes a lower interlayer insulating layer disposed on a semiconductor substrate. The region also includes a plurality of conductive plugs disposed through the lower interlayer insulating layer. The region also includes a phase changeable material pattern operably disposed on the lower interlayer insulating layer, the phase changeable pattern covering at least two of the plurality of conductive plugs, wherein the phase changeable material pattern includes a plurality of first regions in contact with one or more of the plurality of conductive plugs and at least one second region interposed between the plurality of the first regions, wherein the at least one second region has a lower thermal conductivity than the plurality of first regions. The phase changeable memory cell array region also includes an upper interlayer insulating layer covering at least one of the phase changeable material pattern and the lower interlayer insulating layer. The region also includes conductive patterns disposed through the upper interlayer insulating layer and electrically connected to a plurality of predetermined regions of the plurality of first regions.

    摘要翻译： 相变存储单元阵列区域包括设置在半导体衬底上的下层间绝缘层。 该区域还包括穿过下层间绝缘层设置的多个导电插塞。 所述区域还包括可操作地设置在所述下层间绝缘层上的可相变材料图案，所述相变图案覆盖所述多个导电插塞中的至少两个，其中所述相变材料图案包括多个与第 多个导电插塞中的多个和插入在多个第一区域之间的至少一个第二区域，其中至少一个第二区域具有比多个第一区域更低的热导率。 相变存储单元阵列区域还包括覆盖相变材料图案和下层间绝缘层中的至少一个的上层间绝缘层。 该区域还包括通过上层间绝缘层设置并电连接到多个第一区域中的多个预定区域的导电图案。

    Phase changeable memory cell array region and method of forming the same
    18.
    发明申请
    Phase changeable memory cell array region and method of forming the same 有权
    相变存储单元阵列区域及其形成方法

    公开(公告)号：US20070111440A1

    公开(公告)日：2007-05-17

    申请号：US11581012

    申请日：2006-10-16

    申请人： Hyeong-Geun An ,  Hideki Horii ,  Sang-Yeol Kang

    发明人： Hyeong-Geun An ,  Hideki Horii ,  Sang-Yeol Kang

    IPC分类号： H01L21/00 ,  H01L21/336 ,  H01L29/94

    CPC分类号： H01L45/144 ,  H01L27/2436 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1293 ,  H01L45/165 ,  H01L45/1666

    摘要： A phase changeable memory cell array region includes a lower interlayer insulating layer disposed on a semiconductor substrate. The region also includes a plurality of conductive plugs disposed through the lower interlayer insulating layer. The region also includes a phase changeable material pattern operably disposed on the lower interlayer insulating layer, the phase changeable pattern covering at least two of the plurality of conductive plugs, wherein the phase changeable material pattern includes a plurality of first regions in contact with one or more of the plurality of conductive plugs and at least one second region interposed between the plurality of the first regions, wherein the at least one second region has a lower thermal conductivity than the plurality of first regions. The phase changeable memory cell array region also includes an upper interlayer insulating layer covering at least one of the phase changeable material pattern and the lower interlayer insulating layer. The region also includes conductive patterns disposed through the upper interlayer insulating layer and electrically connected to a plurality of predetermined regions of the plurality of first regions.

    摘要翻译： 相变存储单元阵列区域包括设置在半导体衬底上的下层间绝缘层。 该区域还包括穿过下层间绝缘层设置的多个导电插塞。 所述区域还包括可操作地设置在所述下层间绝缘层上的可相变材料图案，所述相变图案覆盖所述多个导电插塞中的至少两个，其中所述相变材料图案包括多个与第 多个导电插塞中的多个和插入在多个第一区域之间的至少一个第二区域，其中至少一个第二区域具有比多个第一区域更低的热导率。 相变存储单元阵列区域还包括覆盖相变材料图案和下层间绝缘层中的至少一个的上层间绝缘层。 该区域还包括通过上层间绝缘层设置并电连接到多个第一区域中的多个预定区域的导电图案。

    Phase changeable memory cell array region and method of forming the same
    19.
    发明授权
    Phase changeable memory cell array region and method of forming the same 有权
    相变存储单元阵列区域及其形成方法

    公开(公告)号：US08039298B2

    公开(公告)日：2011-10-18

    申请号：US12617782

    申请日：2009-11-13

    申请人： Hyeong-Geun An ,  Hideki Horii ,  Sang-Yeol Kang

    发明人： Hyeong-Geun An ,  Hideki Horii ,  Sang-Yeol Kang

    IPC分类号： H01L21/06 ,  H01L21/00 ,  G11C11/00

    CPC分类号： H01L45/144 ,  H01L27/2436 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1293 ,  H01L45/165 ,  H01L45/1666

    摘要： A phase changeable memory cell array region includes a lower interlayer insulating layer disposed on a semiconductor substrate. The region also includes a plurality of conductive plugs disposed through the lower interlayer insulating layer. The region also includes a phase changeable material pattern operably disposed on the lower interlayer insulating layer, the phase changeable pattern covering at least two of the plurality of conductive plugs, wherein the phase changeable material pattern includes a plurality of first regions in contact with one or more of the plurality of conductive plugs and at least one second region interposed between the plurality of the first regions, wherein the at least one second region has a lower thermal conductivity than the plurality of first regions. The phase changeable memory cell array region also includes an upper interlayer insulating layer covering at least one of the phase changeable material pattern and the lower interlayer insulating layer. The region also includes conductive patterns disposed through the upper interlayer insulating layer and electrically connected to a plurality of predetermined regions of the plurality of first regions.

    摘要翻译： 相变存储单元阵列区域包括设置在半导体衬底上的下层间绝缘层。 该区域还包括穿过下层间绝缘层设置的多个导电插塞。 所述区域还包括可操作地设置在所述下层间绝缘层上的可相变材料图案，所述相变图案覆盖所述多个导电插塞中的至少两个，其中所述相变材料图案包括多个与第 多个导电插塞中的多个和插入在多个第一区域之间的至少一个第二区域，其中至少一个第二区域具有比多个第一区域更低的热导率。 相变存储单元阵列区域还包括覆盖相变材料图案和下层间绝缘层中的至少一个的上层间绝缘层。 该区域还包括通过上层间绝缘层设置并电连接到多个第一区域中的多个预定区域的导电图案。