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    Methods of forming multi-level cell of semiconductor memory
    1.
    发明申请
    Methods of forming multi-level cell of semiconductor memory 有权
    形成半导体存储器多级单元的方法

    公开(公告)号：US20100093130A1

    公开(公告)日：2010-04-15

    申请号：US12587772

    申请日：2009-10-13

    申请人： Gyu-Hwan Oh ,  Hyeong-Geun An ,  Soon-Oh Park ,  Dong-Ho Ahn ,  Young-Lim Park

    发明人： Gyu-Hwan Oh ,  Hyeong-Geun An ,  Soon-Oh Park ,  Dong-Ho Ahn ,  Young-Lim Park

    IPC分类号： H01L21/06

    CPC分类号： H01L45/141 ,  H01L27/2409 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/144 ,  H01L45/1666 ,  H01L45/1683

    摘要： Provided is a method of forming a semiconductor memory cell in which in order to store two bits or more data in a memory cell, three or more bottom electrode contacts (BECs) and phase-change materials (GST) have a parallel structure on a single contact plug (CP) and set resistances are changed depending on thicknesses (S), lengths (L) or resistivities (ρ) of the three or more bottom electrode contacts, so that a reset resistance and three different set resistances enable data other than in set and reset states to be stored. Also, a method of forming a memory cell in which three or more phase-change materials (GST) have a parallel structure on a single bottom electrode contact, and the phase-change materials have different set resistances depending on composition ratio or type, so that four or more different resistances can be implemented is provided.

    摘要翻译： 提供了一种形成半导体存储单元的方法，其中为了在存储单元中存储两个或更多个数据，三个或更多个底部电极触点（BEC）和相变材料（GST）在单个存储单元上具有并联结构 接触插头（CP）和设定电阻根据三个或更多个底部电极触点的厚度（S），长度（L）或电阻率（＆rgr）而改变，因此复位电阻和三种不同的设定电阻使数据不能 在设置和复位状态下存储。 此外，形成其中三个或更多个相变材料（GST）在单个底部电极接触上具有平行结构的存储单元的方法，并且相变材料根据组成比或类型具有不同的设定电阻，因此 可以实现四个或更多个不同的电阻。

    Methods of forming multi-level cell of semiconductor memory
    2.
    发明授权
    Methods of forming multi-level cell of semiconductor memory 有权
    形成半导体存储器多级单元的方法

    公开(公告)号：US08187918B2

    公开(公告)日：2012-05-29

    申请号：US12587772

    申请日：2009-10-13

    申请人： Gyu-Hwan Oh ,  Hyeung-Geun An ,  Soon-Oh Park ,  Dong-Ho Ahn ,  Young-Lim Park

    发明人： Gyu-Hwan Oh ,  Hyeung-Geun An ,  Soon-Oh Park ,  Dong-Ho Ahn ,  Young-Lim Park

    IPC分类号： H01L21/06

    CPC分类号： H01L45/141 ,  H01L27/2409 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/144 ,  H01L45/1666 ,  H01L45/1683

    摘要： Provided is a method of forming a semiconductor memory cell in which in order to store two bits or more data in a memory cell, three or more bottom electrode contacts (BECs) and phase-change materials (GST) have a parallel structure on a single contact plug (CP) and set resistances are changed depending on thicknesses (S), lengths (L) or resistivities (ρ) of the three or more bottom electrode contacts, so that a reset resistance and three different set resistances enable data other than in set and reset states to be stored. Also, a method of forming a memory cell in which three or more phase-change materials (GST) have a parallel structure on a single bottom electrode contact, and the phase-change materials have different set resistances depending on composition ratio or type, so that four or more different resistances can be implemented is provided.

    摘要翻译： 提供了一种形成半导体存储单元的方法，其中为了在存储单元中存储两个或更多个数据，三个或更多个底部电极触点（BEC）和相变材料（GST）在单个存储单元上具有并联结构 接触插头（CP）和设定电阻根据三个或更多个底部电极触点的厚度（S），长度（L）或电阻率（＆rgr）而改变，因此复位电阻和三种不同的设定电阻使数据不能 在设置和复位状态下存储。 此外，形成其中三个或更多个相变材料（GST）在单个底部电极接触上具有平行结构的存储单元的方法，并且相变材料根据组成比或类型具有不同的设定电阻，因此 可以实现四个或更多个不同的电阻。

    Phase-changeable memory device and method of manufacturing the same
    4.
    发明授权
    Phase-changeable memory device and method of manufacturing the same 有权
    相变存储器件及其制造方法

    公开(公告)号：US07563639B2

    公开(公告)日：2009-07-21

    申请号：US11733131

    申请日：2007-04-09

    申请人： Hee-Ju Shin ,  Jong-Chan Shin ,  Soon-Oh Park ,  Hyeong-Geun An ,  Han-Bong Ko

    发明人： Hee-Ju Shin ,  Jong-Chan Shin ,  Soon-Oh Park ,  Hyeong-Geun An ,  Han-Bong Ko

    IPC分类号： H01L21/06

    CPC分类号： H01L45/06 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/143 ,  H01L45/144 ,  H01L45/1683

    摘要： In a semiconductor memory device and a method of manufacturing the same, an insulating layer is formed on a substrate having a logic region on which a first pad is provided and a cell region on which a second pad and a lower electrode are subsequently provided. The insulating layer is etched to be a first insulating layer pattern having a first opening exposing the first pad. A first plug is formed in the first opening. The first insulating layer pattern where the first plug is formed is etched to be a second insulating layer pattern having a second opening exposing the lower electrode. A second plug including a phase-changeable material is formed in the second opening. A conductive wire and an upper electrode are formed on the first plug and the second plug, respectively.

    摘要翻译： 在半导体存储器件及其制造方法中，在具有设置有第一焊盘的逻辑区域的衬底上形成绝缘层，并且随后设置有第二焊盘和下电极的单元区域。 绝缘层被蚀刻成具有第一开口的第一绝缘层图案，该第一开口露出第一焊盘。 第一插头形成在第一开口中。 将形成有第一插塞的第一绝缘层图案蚀刻成具有暴露下电极的第二开口的第二绝缘层图案。 包括相变材料的第二插头形成在第二开口中。 导线和上电极分别形成在第一插头和第二插头上。

    FRAM and method of fabricating the same
    5.
    发明授权
    FRAM and method of fabricating the same 有权
    FRAM及其制造方法

    公开(公告)号：US06686620B2

    公开(公告)日：2004-02-03

    申请号：US10109432

    申请日：2002-03-27

    申请人： Hyeong-Geun An ,  Soon-Oh Park

    发明人： Hyeong-Geun An ,  Soon-Oh Park

    IPC分类号： H01L27108

    CPC分类号： H01L28/65 ,  H01L27/10852 ,  H01L27/10882 ,  H01L28/57

    摘要： A FRAM having a ferroelectric capacitor comprises a cylindrical type bottom electrode. A ferroelectric film is thinly stacked over the bottom electrode, and the first portion of the top electrode formed over and conformal to the ferroelectric film. A void that is left between sidewalls of the first portion of the electrode over the ferroelectric film is then filled with fill material for a fill layer. The fill material of the fill layer is then planarized to be level with and expose an upper surface of the first portion of the top electrode. A second portion of the top electrode is then formed over the fill layer and in contact with the exposed, e.g. peripheral regions of the first portion of the electrode. The fill material of the fill layer may be formed of polysilicon, silicon oxide or other material such as another metal. Additionally, the fill layer may be formed of a fill material that has a superior gap fill capability or of a material that has a low stress relationship with respect to the capacitor's top metal.

    摘要翻译： 具有铁电电容器的FRAM包括圆柱形底部电极。 铁电体薄膜层叠在底部电极上，并且顶部电极的第一部分形成在铁电膜上并与其形成共形。 然后，在铁电体膜上的电极的第一部分的侧壁之间留下的空隙填充有用于填充层的填充材料。 然后将填充层的填充材料平坦化以与顶部电极的第一部分的上表面平齐并暴露。 然后，顶部电极的第二部分形成在填充层之上并与暴露的例如电极接触。 电极的第一部分的周边区域。 填充层的填充材料可以由多晶硅，氧化硅或其它材料例如另一种金属形成。 另外，填充层可以由具有优异间隙填充能力的填充材料或与电容器的顶部金属具有低应力关系的材料形成。

    Method of forming a phase change material layer pattern and method of manufacturing a phase change memory device
    9.
    发明授权
    Method of forming a phase change material layer pattern and method of manufacturing a phase change memory device 有权
    形成相变材料层图案的方法和制造相变存储器件的方法

    公开(公告)号：US08865558B2

    公开(公告)日：2014-10-21

    申请号：US13543905

    申请日：2012-07-09

    申请人： Jeong-Hee Park ,  Soon-Oh Park ,  Jung-Hwan Park ,  Jin-Ho Oh

    发明人： Jeong-Hee Park ,  Soon-Oh Park ,  Jung-Hwan Park ,  Jin-Ho Oh

    IPC分类号： H01L47/00 ,  H01L45/00

    CPC分类号： H01L45/06 ,  H01L45/141 ,  H01L45/1683

    摘要： A method of forming a phase change material layer pattern includes forming a phase change material layer partially filling an opening through an insulating interlayer. A plasma treatment process is performed on the phase change material layer to remove an oxide layer on a surface of the phase change material layer. A heat treatment process is performed on the phase change material layer to remove a void or a seam in the phase change material layer, sufficiently filling the opening.

    摘要翻译： 形成相变材料层图案的方法包括：通过绝缘中间层形成部分填充开口的相变材料层。 在相变材料层上进行等离子体处理工艺以去除相变材料层的表面上的氧化物层。 在相变材料层上进行热处理工艺以去除相变材料层中的空隙或接缝，充分填充开口。

    Nonvolatile memory devices, nonvolatile memory cells and methods of manufacturing nonvolatile memory devices
    10.
    发明授权
    Nonvolatile memory devices, nonvolatile memory cells and methods of manufacturing nonvolatile memory devices 有权
    非易失性存储器件，非易失性存储器单元以及制造非易失性存储器件的方法

    公开(公告)号：US09343672B2

    公开(公告)日：2016-05-17

    申请号：US13442595

    申请日：2012-04-09

    申请人： Chan-Jin Park ,  Sun-Jung Kim ,  Soon-Oh Park ,  Hyun-Su Ju ,  Soo-Doo Chae

    发明人： Chan-Jin Park ,  Sun-Jung Kim ,  Soon-Oh Park ,  Hyun-Su Ju ,  Soo-Doo Chae

    IPC分类号： H01L45/00 ,  H01L27/24

    CPC分类号： H01L45/1253 ,  H01L27/2472 ,  H01L27/249 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/146

    摘要： A nonvolatile memory cell includes first and second interlayer insulating films which are separated from each other and are stacked sequentially, a first electrode which penetrates the first interlayer insulating film and the second interlayer insulating film, a resistance change film which is formed along a side surface of the first electrode and extends parallel to the first electrode, and a second electrode which is formed between the first interlayer insulating film and the second interlayer insulating film. The second electrode includes a conductive film which is made of metal and a diffusion preventing film which prevents diffusion of a conductive material contained in the conductive film.

    摘要翻译： 非易失性存储单元包括彼此分离并依次堆叠的第一和第二层间绝缘膜，穿过第一层间绝缘膜和第二层间绝缘膜的第一电极，沿着侧表面形成的电阻变化膜 并且平行于第一电极延伸，以及形成在第一层间绝缘膜和第二层间绝缘膜之间的第二电极。 第二电极包括由金属制成的导电膜和防止导电膜中包含的导电材料扩散的防扩散膜。