Abstract:
A resistive memory system, a driver circuit thereof and a method for setting resistances thereof are provided. The resistive memory system includes a memory array, a row selection circuit, a first control circuit and a second control circuit. The memory array has a plurality of resistive memory cells. The row selection circuit is used for activating the resistive memory cells. The first control circuit and the second control circuit are coupled to the resistive memory cells. When each of resistive memory cells is set, the first control circuit and the second control circuit respectively provide a set voltage and a ground voltage to the each of resistive memory cells to form a set current, and the set current is clamped by at least one of the first control circuit and the second control circuit.
Abstract:
A through silicon via (TSV) repair circuit is provided. The TSV repair circuit includes at least two transmission control switches and at least two transmission path modules. Two transmission control switches transmit an input signal of a first chip or a second chip to one of two terminals in each of the transmission path modules according to a switch signal. Each transmission path module includes at least two data path circuits and corresponding TSVs. Each data path circuit includes an input driving circuit, a short-circuit detection circuit and a leakage current cancellation circuit. The short-circuit detection circuit detects whether to detect whether short-circuit on the TSV and a silicon substrate is present and generate a short-circuit detection output signal. The leakage current cancellation circuit to avoid a leakage current generated by a first level voltage to flow into the silicon substrate according to the short-circuit detection output signal.
Abstract:
A varactor is provided. A substrate includes a first surface, a second surface and a first opening and a second opening in the substrate. A conductive material is filling the first and second openings, to form a first through-wafer via (TWV) and a second through-wafer via. A first capacitor is coupled between the first through-wafer via and a first terminal. A second capacitor is coupled between the second through-wafer via and a second terminal. A capacitance of a depletion-region capacitor between the first through-wafer via and the second through-wafer via is determined by a bias voltage applied to the first through-wafer via and the second through-wafer via.
Abstract:
A through silicon via (TSV) repair circuit of a semiconductor apparatus is provided. The TSV repair circuit includes a first chip, at least one second chip, at least two TSVs, at least two data path circuits, and an output logic circuit. Each data path circuit includes an input driving circuit, a short-circuit detection circuit, a bias circuit, and a leakage current cancellation circuit. The input driving circuit transforms an input signal into a pending signal and transmits the pending signal to a first terminal of the corresponding TSV. The short-circuit detection circuit detects a short circuit between the corresponding TSV and a silicon substrate according to the input signal and the first terminal of the TSV and generates a short-circuit detection output signal. The leakage current cancellation circuit prevents a leakage current produced by a first level voltage from entering the silicon substrate according to the short-circuit detection output signal.
Abstract:
A varactor is provided. A substrate includes a first surface, a second surface and a first opening and a second opening in the substrate. A conductive material is filling the first and second openings, to form a first through-wafer via (TWV) and a second through-wafer via. A first capacitor is coupled between the first through-wafer via and a first terminal. A second capacitor is coupled between the second through-wafer via and a second terminal. A capacitance of a depletion-region capacitor between the first through-wafer via and the second through-wafer via is determined by a bias voltage applied to the first through-wafer via and the second through-wafer via.