公开(公告)号：US20170019104A1

公开(公告)日：2017-01-19

申请号：US14801868

申请日：2015-07-17

Applicant: Infineon Technologies AG

Inventor： Thomas Kuenemund

IPC: H03K19/003 ,  H01L21/8234

CPC classification number: H03K19/00315 ,  H01L21/823475

Abstract: A method for manufacturing a digital circuit is described including forming a plurality of field effect transistor pairs, connecting the field effect transistors of the field effect transistor pairs such that in response to a first transition from a first state of two nodes of the digital circuit and in response to a second transition from a second state of the nodes of the digital circuit the nodes each have an undefined logic state when, for each field effect transistor pair, the threshold voltages of the field effect transistors of the field effect transistor pair are equal and setting the threshold voltages of the field effect transistors of the field effect transistor pairs such that the nodes each have a predetermined defined logic state in response to the first transition and in response to the second transition.

Abstract translation: 描述了一种制造数字电路的方法，包括形成多个场效应晶体管对，连接场效应晶体管对的场效应晶体管，使得响应于来自数字电路的两个节点的第一状态的第一转变和 响应于来自数字电路的节点的第二状态的第二过渡，节点各自具有未定义的逻辑状态，当对于每个场效应晶体管对，场效应晶体管对的场效应晶体管的阈值电压相等时 以及设置场效应晶体管对的场效应晶体管的阈值电压，使得每个节点响应于第一转变和响应于第二转变而具有预定的定义逻辑状态。

公开(公告)号：US09432014B2

公开(公告)日：2016-08-30

申请号：US13956445

申请日：2013-08-01

Applicant: Infineon Technologies AG

Inventor： Thomas Kuenemund ,  Artur Wroblewski

IPC: H03K17/22 ,  G06F1/26 ,  G06F1/32

CPC classification number: H03K17/223 ,  G06F1/263 ,  G06F1/3296 ,  Y02D10/172

Abstract: In accordance with one embodiment, a circuit arrangement is provided including a circuit having a first terminal for a first supply potential and a second terminal for a second supply potential, wherein the first terminal is coupled to the first supply potential; a switch, by means of which the second terminal can be coupled to the second supply potential; a voltage source coupled to the second terminal; and a control device designed to open the switch in reaction to receiving a turn-off signal in an operating mode in which the switch is closed, and subsequently to control the voltage source in such a way that it varies the potential of the second terminal in the direction of the first supply potential.

Abstract translation: 根据一个实施例，提供一种电路装置，其包括具有用于第一电源电位的第一端子和用于第二电源电位的第二端子的电路，其中第一端子耦合到第一电源电位; 开关，通过该开关，第二端子可以耦合到第二电源电位; 耦合到所述第二端子的电压源; 以及控制装置，其设计成在开关闭合的操作模式中打开开关以响应于接收关断信号，并且随后以这样的方式控制电压源，使得其改变第二端子的电位 第一个供应电位的方向。

公开(公告)号：US09407255B2

公开(公告)日：2016-08-02

申请号：US13947156

申请日：2013-07-22

Applicant: Infineon Technologies AG

Inventor： Thomas Kuenemund

IPC: H03B1/00 ,  H03K3/00 ,  H03K17/30 ,  G11C7/20 ,  G11C29/02

CPC classification number: H03K17/30 ,  G11C7/20 ,  G11C29/021 ,  G11C29/028 ,  G11C2207/2227

Abstract: In accordance with various embodiments, a circuit is provided, including an output node, a first potential varying stage, which is designed to couple the output node to a supply potential in reaction to an input signal, and a second potential varying stage, which is designed to couple the output node to the supply potential if the difference between the potential of the output node and the supply potential lies below a predefined threshold value.

Abstract translation: 根据各种实施例，提供一种电路，包括输出节点，被设计成将输出节点耦合到与输入信号反应的电源电位的第一电位变化级和第二电位变化级，第二电位变化级是 如果输出节点的电位和电源电位之间的差异低于预定义的阈值，则将输出节点耦合到电源电位。

公开(公告)号：US20150303927A1

公开(公告)日：2015-10-22

申请号：US14254913

申请日：2014-04-17

Applicant: Infineon Technologies AG

Inventor： Thomas Kuenemund ,  Bernhard Lippmann

IPC: H03K19/21 ,  H01L21/8234

CPC classification number: H03K19/215 ,  H01L23/576 ,  H01L27/0203 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/092 ,  H01L27/11807 ,  H01L2924/0002 ,  H03K19/17768 ,  H01L2924/00

Abstract: According to one embodiment, a chip is described comprising a plurality of supply lines delimiting a plurality of cell areas and a gate comprising a first transistor and a second transistor, wherein the first transistor is located in a first cell area of the plurality of cell areas and the second transistor is located in a second cell area of the plurality of cell areas such that a supply line of the plurality of supply lines lies between the first cell area and the second cell area.

Abstract translation: 根据一个实施例，描述了芯片，其包括限定多个单元区域的多个供电线和包括第一晶体管和第二晶体管的栅极，其中第一晶体管位于多个单元区域的第一单元区域中 并且所述第二晶体管位于所述多个单元区域的第二单元区域中，使得所述多条电源线的供电线位于所述第一单元区域和所述第二单元区域之间。

公开(公告)号：US20130246881A1

公开(公告)日：2013-09-19

申请号：US13803324

申请日：2013-03-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Rainer Goettfert ,  Gerd Dirscherl ,  Berndt Gammel ,  Thomas Kuenemund

IPC: H03M13/00

CPC classification number: H03M13/00 ,  H03M13/03 ,  H03M13/3707 ,  H04L1/0045 ,  H04L9/0866 ,  H04L9/3278 ,  H04L2209/34

Abstract: A method for reconstructing a physically uncloneable function (PUF) A for use in an electronic device is provided. The method includes generating a potentially erroneous PUF At and performing a preliminary correction of the potentially erroneous PUF At by means of a stored correction vector Deltat-1, to obtain a preliminarily corrected PUF Bt. The PUF A is reconstructed from the preliminarily corrected PUF Bt by means of an error correction algorithm. A corresponding apparatus is also provided.

Abstract translation: 提供了用于重建用于电子设备的物理上不可克隆功能（PUF）A的方法。 该方法包括产生潜在错误的PUF At，并通过存储的校正矢量Deltat-1对潜在错误的PUF At进行初步校正，以获得预先校正的PUF Bt。 通过纠错算法从预先校正的PUF Bt重建PUF A。 还提供了相应的装置。

公开(公告)号：US20210288633A1

公开(公告)日：2021-09-16

申请号：US17198477

申请日：2021-03-11

Applicant: Infineon Technologies AG

Inventor： Thomas Kuenemund ,  Anton Huber

IPC: H03K3/037

Abstract: A master-slave D flip-flop is disclosed having gates configured to supply two second intermediate signals as a function of first intermediate signals and a clock signal, and a slave circuit connected to a transfer circuit to form at least one output signal of the flip-flop from the second intermediate signals. The slave circuit is configured, when the second intermediate signals have, after a preceding pair of states, a predetermined pair of states, to maintain the at least one output signal as given by the preceding pair of states. The transfer circuit has a control input and is configured to generate the second intermediate signals to have the predetermined pair of states in response to a predetermined control signal state at the control input.

公开(公告)号：US20210143802A1

公开(公告)日：2021-05-13

申请号：US17070086

申请日：2020-10-14

Applicant: Infineon Technologies AG

Inventor： Thomas Kuenemund ,  Thomas Poeppelmann

IPC: H03K3/038 ,  H04L9/30 ,  H04L29/06 ,  H04L9/08 ,  H04L9/06

Abstract: A storage element that is operable based on a system clock signal, the storage element including a clock gating circuitry configured to generate a gated clock signal based on at least one Boolean signal and the system clock signal or a preprocessed system clock signal, wherein the clock gating circuitry comprises physical connections of small capacitance such that tapping of at least one of the physical connections results in a hold-time violation. Also, a hardware-based cryptography accelerator or a secured processing system including at least one such storage element, and a method for operating at least one storage element.

公开(公告)号：US20210066216A1

公开(公告)日：2021-03-04

申请号：US17004036

申请日：2020-08-27

Applicant: Infineon Technologies AG

Inventor： Thomas Kuenemund

IPC: H01L23/00 ,  H01L27/092

Abstract: A physically obfuscated circuit (POC) circuit including a plurality of subcircuits, each comprising at least one p-channel field effect transistor (FET) and at least one n-channel FET, connected such that the at least one n-channel FET, if supplied with an upper supply potential at its gate, supplies a lower supply potential to the gate of the at least one p-channel FET and the at least one p-channel FET, if supplied with the lower supply potential at its gate, supplies the upper supply potential to the gate of the at least one n-channel FET.

公开(公告)号：US20210066215A1

公开(公告)日：2021-03-04

申请号：US17002829

申请日：2020-08-26

Applicant: Infineon Technologies AG

Inventor： Thomas Kuenemund

IPC: H01L23/00 ,  H01L27/02 ,  H01L27/092 ,  H01L23/528

Abstract: A semiconductor chip may have at least one p-channel field effect transistor (FET), at least one n-channel FET, a first and a second power supply terminal, wherein the at least one n-channel FET, if supplied with the upper supply potential at its gate, supplies the lower supply potential to the gate of the at least one p-channel FET and the at least one p-channel FET, if supplied with the lower supply potential at its gate, supplies the upper supply potential to the gate of the at least one n-channel FET, a precharge circuit to precharge the circuit to a first state, and a detection circuit configured to output an alarm signal if the circuit enters a second state.

公开(公告)号：US10600742B2

公开(公告)日：2020-03-24

申请号：US16116270

申请日：2018-08-29

Applicant: Infineon Technologies AG

Inventor： Thomas Kuenemund ,  Hans Friedinger

IPC: H01L23/552 ,  G06F21/75 ,  H01L23/00 ,  H03K3/037 ,  H03K3/356 ,  G06F21/87 ,  H01L27/144

Abstract: A chip having a substrate region having a substrate contact, an RS latch having two complementary nodes representing a storage state of the RS latch, a control circuit having a control input and configured to connect one of the complementary nodes to a supply potential depending on a potential at the control input, wherein the control input is connected to the substrate contact, and an output circuit connected to an output of the RS latch and configured to trigger an alarm depending on the storage state of the RS latch.