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    Selective rasterization
    13.
    发明授权
    Selective rasterization 有权

    公开(公告)号：US10164458B2

    公开(公告)日：2018-12-25

    申请号：US15492112

    申请日：2017-04-20

    Applicant: Intel Corporation

    Inventor： Tomas G. Akenine-Moller ,  Carl J. Munkberg ,  Franz P. Clarberg

    IPC: G06T11/40 ,  H02J7/00 ,  G01R19/00 ,  H02J7/02 ,  H02J7/04

    Abstract: According to one embodiment, a given tile, made up of pixels or samples, may be of any shape, including a square shape. These pixels may contain colors, depths, stencil values, and other values. Each tile may be further augmented with a single bit, referred to herein as a render bit. In one embodiment, if the render bit is one, then everything is rendered as usual within the tile. However, if the render bit is zero, then nothing is rasterized to this tile and, correspondingly, depth tests, pixel shading, frame buffer accesses, and multi-sampled anti-aliasing (MSAA) resolves are not done for this tile. In other embodiments, some operations may be done nevertheless, but at least one operation is avoided based on the render bit. Of course, the render bits may be switched such that the bit zero indicates that everything should be rendered and the bit one indicates more limited rendering.

    Selective Rasterization
    14.
    发明申请
    Selective Rasterization 审中-公开

    公开(公告)号：US20170264106A1

    公开(公告)日：2017-09-14

    申请号：US15605016

    申请日：2017-05-25

    Applicant: Intel Corporation

    Inventor： Tomas G. Akenine-Moller ,  Carl J. Munkberg ,  Franz P. Clarberg

    IPC: H02J7/00 ,  G01R19/00 ,  H02J7/02 ,  H02J7/04

    CPC classification number: H02J7/007 ,  G01R19/0092 ,  G06T11/40 ,  H02J7/0052 ,  H02J7/0055 ,  H02J7/025 ,  H02J7/045

    Abstract: According to one embodiment, a given tile, made up of pixels or samples, may be of any shape, including a square shape. These pixels may contain colors, depths, stencil values, and other values. Each tile may be further augmented with a single bit, referred to herein as a render bit. In one embodiment, if the render bit is one, then everything is rendered as usual within the tile. However, if the render bit is zero, then nothing is rasterized to this tile and, correspondingly, depth tests, pixel shading, frame buffer accesses, and multi-sampled anti-aliasing (MSAA) resolves are not done for this tile. In other embodiments, some operations may be done nevertheless, but at least one operation is avoided based on the render bit. Of course, the render bits may be switched such that the bit zero indicates that everything should be rendered and the bit one indicates more limited rendering.

    Depth of field rasterization
    16.
    发明授权
    Depth of field rasterization 有权
    景深光栅化

    公开(公告)号：US09317964B2

    公开(公告)日：2016-04-19

    申请号：US14688107

    申请日：2015-04-16

    Applicant: Intel Corporation

    Inventor： Tomas G. Akenine-Moller ,  Carl J. Munkberg ,  Jon N. Hasselgren ,  Robert M. Toth

    IPC: G06T15/40 ,  G06T17/20

    CPC classification number: G06T15/40 ,  G06T17/20

    Abstract: Depth of field may be rasterized by culling half-space regions on a lens from which a triangle to be rendered is not visible. Then, inside tests are only performed on the remaining unculled half-space regions. Separating planes between the triangle to be rendered and the tile being processed can be used to define the half-space regions.

    Abstract translation: 可以通过剔除要被渲染的三角形不可见的透镜上的半空间区域来光栅化景深。 然后，内部测试仅对剩余的未被空白的半空间区域进行。 要渲染的三角形和正在处理的瓷砖之间的分离平面可用于定义半空间区域。

    Filtered Shadow Mapping
    17.
    发明申请
    Filtered Shadow Mapping 有权
    过滤阴影映射

    公开(公告)号：US20160093098A1

    公开(公告)日：2016-03-31

    申请号：US14575197

    申请日：2014-12-18

    Applicant: Intel Corporation

    Inventor： Magnus Andersson ,  Jon N. Hasselgren ,  Carl J. Munkberg ,  Tomas Akenine-Moller

    IPC: G06T15/80 ,  G06T7/00

    CPC classification number: G06T7/215 ,  G06T11/40 ,  G06T13/20 ,  G06T15/04 ,  G06T15/60 ,  G06T2215/12

    Abstract: A layered, filtered shadow mapping algorithm may be used for motion blurred shadows. The algorithm is divided into two passes, namely a shadow pass and a lighting pass. The shadow pass renders the scene using stochastic rasterization and generates a time-dependent shadow map augmented with per-sample motion vectors. The subsequent lighting pass renders the scene from the camera's point of view, and performs a shadow query for each sample seen from the camera.

    Abstract translation: 分层的，过滤的阴影映射算法可用于运动模糊阴影。 该算法分为两个通道，即阴影通道和照明通道。 阴影通过使用随机光栅化渲染场景，并且生成以逐采样运动矢量增强的时间依赖的阴影图。 随后的照明通道从相机的角度呈现场景，并对从相机看到的每个样品执行阴影查询。

    Minimum/maximum and bitwise and/or based coarse stencil test
    19.
    发明授权
    Minimum/maximum and bitwise and/or based coarse stencil test 有权

    公开(公告)号：US10453170B2

    公开(公告)日：2019-10-22

    申请号：US15260570

    申请日：2016-09-09

    Applicant: Intel Corporation

    Inventor： Robert M. Toth ,  Carl J. Munkberg ,  Jon N. Hasselgren

    IPC: G06T1/60 ,  G06T1/20 ,  G06T15/00

    Abstract: Methods and apparatus relating to techniques for provision of minimum or maximum and bitwise logic AND or logic OR based coarse stencil tests are described. In an embodiment, metadata (corresponding to a plurality of pixels) is stored in memory. One or more operations are performed on the metadata to generate a stencil result. The one or more operations comprise a bitwise intersection operation or a bitwise union operation and/or a minimum operation or maximum operation. Other embodiments are also disclosed and claimed.

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