公开(公告)号：US20210202319A1

公开(公告)日：2021-07-01

申请号：US16728903

申请日：2019-12-27

Applicant: Intel Corporation

Inventor： Ashish Agrawal ,  Gilbert Dewey ,  Cheng-Ying Huang ,  Willy Rachmady ,  Anand Murthy ,  Ryan Keech ,  Cory Bomberger

IPC: H01L21/822 ,  H01L27/12 ,  H01L29/08 ,  H01L23/522 ,  H01L29/417 ,  H01L21/8238

Abstract: A monolithic three-dimensional integrated circuit may include multiple transistor levels separated by one or more levels of metallization. An upper level transistor structure may include monocrystalline source and drain material epitaxially grown from a monocrystalline channel material at a temperature low enough to avoid degradation of a lower level transistor structure and/or degradation of one or more low-k dielectric materials between the transistor levels. A highly conductive n-type silicon source and drain material may be selectively deposited at low temperatures with a high pressure CVD process. Multiple crystals of source drain material arranged in a vertically stacked multi-channel transistor structure may be contacted by a single contact metallization.

公开(公告)号：US12027585B2

公开(公告)日：2024-07-02

申请号：US18110315

申请日：2023-02-15

Applicant: Intel Corporation

Inventor： Cory Bomberger ,  Anand Murthy ,  Suresh Vishwanath

IPC: H01L29/08 ,  B82Y10/00 ,  H01L21/02 ,  H01L21/8234 ,  H01L23/00 ,  H01L27/088 ,  H01L27/092 ,  H01L29/06 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/36 ,  H01L29/40 ,  H01L29/417 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78

CPC classification number: H01L29/0847 ,  H01L21/02532 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823475 ,  H01L24/09 ,  H01L24/17 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/16 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858 ,  H01L2224/0401

Abstract: Integrated circuit structures having source or drain structures with low resistivity are described. In an example, integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. A gate stack is over the upper fin portion of the fin, the gate stack having a first side opposite a second side. A first source or drain structure includes an epitaxial structure embedded in the fin at the first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at the second side of the gate stack. Each epitaxial structure of the first and second source or drain structures include silicon, germanium and boron. The first and second source or drain structures have a resistivity less than or equal to 0.3 mOhm·cm.

公开(公告)号：US20240136277A1

公开(公告)日：2024-04-25

申请号：US18395192

申请日：2023-12-22

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Ryan Keech ,  Cory Bomberger ,  Cheng-Ying Huang ,  Ashish Agrawal ,  Willy Rachmady ,  Anand Murthy

IPC: H01L23/522 ,  H01L21/762 ,  H01L21/768 ,  H01L27/12

CPC classification number: H01L23/5226 ,  H01L21/76251 ,  H01L21/76804 ,  H01L27/1203

Abstract: A device includes a device level having a metallization structure coupled to a semiconductor device and a transistor above the device level. The transistor has a body including a single crystal group III-V or group IV semiconductor material, a source structure on a first portion of the body and a drain structure on a second portion of the body, where the source structure is separate from the drain structure. The transistor further includes a gate structure including a first gate structure portion in a recess in the body and a second gate structure portion between the source structure and the drain structure. A source contact is coupled with the source structure and a drain contact is coupled with the drain structure. The source contact is in contact with the metallization structure in the device level.

公开(公告)号：US11887988B2

公开(公告)日：2024-01-30

申请号：US16529643

申请日：2019-08-01

Applicant: Intel Corporation

Inventor： Ashish Agrawal ,  Jack Kavalieros ,  Anand Murthy ,  Gilbert Dewey ,  Matthew Metz ,  Willy Rachmady ,  Cheng-Ying Huang ,  Cory Bomberger

IPC: H01L27/12 ,  H01L29/08 ,  H01L29/66 ,  H01L29/10 ,  H01L29/417

CPC classification number: H01L27/1207 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/41733 ,  H01L29/66742

Abstract: Thin film transistor structures may include a regrown source or drain material between a channel material and source or drain contact metallization. The source or drain material may be selectively deposited at low temperatures to backfill recesses formed in the channel material. Electrically active dopant impurities may be introduced in-situ during deposition of the source or drain material. The source or drain material may overlap a portion of a gate electrode undercut by the recesses. With channel material of a first composition and source or drain material of a second composition, thin film transistor structures may display low external resistance and high channel mobility.

公开(公告)号：US11532734B2

公开(公告)日：2022-12-20

申请号：US16370449

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Cory Bomberger ,  Anand Murthy ,  Susmita Ghose ,  Zachary Geiger

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/34 ,  H01L29/08 ,  H01L21/02 ,  H01L29/423

Abstract: Gate-all-around integrated circuit structures having germanium nanowire channel structures, and methods of fabricating gate-all-around integrated circuit structures having germanium nanowire channel structures, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires above a fin, each of the nanowires including germanium, and the fin including a defect modification layer on a first semiconductor layer, a second semiconductor layer on the defect modification layer, and a third semiconductor layer on the second semiconductor layer. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires, and a second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires.

公开(公告)号：US11450739B2

公开(公告)日：2022-09-20

申请号：US16131520

申请日：2018-09-14

Applicant: INTEL CORPORATION

Inventor： Glenn Glass ,  Anand Murthy ,  Cory Bomberger ,  Tahir Ghani ,  Jack Kavalieros ,  Siddharth Chouksey ,  Seung Hoon Sung ,  Biswajeet Guha ,  Ashish Agrawal

IPC: H01L29/06 ,  H01L21/82 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/161 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor structure has a substrate including silicon and a layer of relaxed buffer material on the substrate with a thickness no greater than 300 nm. The buffer material comprises silicon and germanium with a germanium concentration from 20 to 45 atomic percent. A source and a drain are on top of the buffer material. A body extends between the source and drain, where the body is monocrystalline semiconductor material comprising silicon and germanium with a germanium concentration of at least 30 atomic percent. A gate structure is wrapped around the body.

公开(公告)号：US20220223519A1

公开(公告)日：2022-07-14

申请号：US17709032

申请日：2022-03-30

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Ryan Keech ,  Cory Bomberger ,  Cheng-Ying Huang ,  Ashish Agrawal ,  Willy Rachmady ,  Anand Murthy

IPC: H01L23/522 ,  H01L21/768 ,  H01L21/762 ,  H01L27/12

Abstract: A device includes a device level having a metallization structure coupled to a semiconductor device and a transistor above the device level. The transistor has a body including a single crystal group III-V or group IV semiconductor material, a source structure on a first portion of the body and a drain structure on a second portion of the body, where the source structure is separate from the drain structure. The transistor further includes a gate structure including a first gate structure portion in a recess in the body and a second gate structure portion between the source structure and the drain structure. A source contact is coupled with the source structure and a drain contact is coupled with the drain structure. The source contact is in contact with the metallization structure in the device level.

公开(公告)号：US11374100B2

公开(公告)日：2022-06-28

申请号：US16022502

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Cory Bomberger ,  Rishabh Mehandru ,  Anupama Bowonder ,  Biswajeet Guha ,  Anand Murthy ,  Tahir Ghani

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L29/08 ,  H01L29/167

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, integrated circuit structures having source or drain structures with a contact etch stop layer are described. In an example, an integrated circuit structure includes a fin including a semiconductor material, the fin having a lower fin portion and an upper fin portion. A gate stack is over the upper fin portion of the fin, the gate stack having a first side opposite a second side. A first epitaxial source or drain structure is embedded in the fin at the first side of the gate stack. A second epitaxial source or drain structure is embedded in the fin at the second side of the gate stack, the first and second epitaxial source or drain structures including a lower semiconductor layer, an intermediate semiconductor layer and an upper semiconductor layer.

公开(公告)号：US12237420B2

公开(公告)日：2025-02-25

申请号：US18643632

申请日：2024-04-23

Applicant: Intel Corporation

Inventor： Cory Bomberger ,  Anand S. Murthy ,  Tahir Ghani ,  Anupama Bowonder

IPC: H01L21/00 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78

Abstract: Fin smoothing, and integrated circuit structures resulting therefrom, are described. For example, an integrated circuit structure includes a semiconductor fin having a protruding fin portion above an isolation structure, the protruding fin portion having substantially vertical sidewalls. The semiconductor fin further includes a sub-fin portion within an opening in the isolation structure, the sub-fin portion having a different semiconductor material than the protruding fin portion. The sub-fin portion has a width greater than or less than a width of the protruding portion where the sub-fin portion meets the protruding portion. A gate stack is over and conformal with the protruding fin portion of the semiconductor fin. A first source or drain region at a first side of the gate stack, and a second source or drain region at a second side of the gate stack opposite the first side of the gate stack.

公开(公告)号：US12159901B2

公开(公告)日：2024-12-03

申请号：US17982459

申请日：2022-11-07

Applicant: Intel Corporation

Inventor： Cory Bomberger ,  Anand Murthy ,  Mark T. Bohr ,  Tahir Ghani ,  Biswajeet Guha

IPC: H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: Gate-all-around integrated circuit structures having source or drain structures with epitaxial nubs, and methods of fabricating gate-all-around integrated circuit structures having source or drain structures with epitaxial nubs, are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires and a second vertical arrangement of horizontal nanowires. A first pair of epitaxial source or drain structures includes vertically discrete portions aligned with the first vertical arrangement of horizontal nanowires. A second pair of epitaxial source or drain structures includes vertically discrete portions aligned with the second vertical arrangement of horizontal nanowires. A conductive contact structure is laterally between and in contact with the one of the first pair of epitaxial source or drain structures and the one of the second pair of epitaxial source or drain structures.