公开(公告)号：US10579464B2

公开(公告)日：2020-03-03

申请号：US15912450

申请日：2018-03-05

Applicant: INTEL CORPORATION

Inventor： Debaleena Das ,  Rajat Agarwal ,  Brian S. Morris

IPC: G06F11/07 ,  G06F3/06 ,  G06F11/10

Abstract: Provided are an apparatus and method to store data from a cache line at locations having errors in a sparing directory. In response to a write operation having write data for locations in one of the cache lines, the write data for a location in the cache line having an error is written to an entry in a sparing directory including an address of the cache line.

公开(公告)号：US09760435B2

公开(公告)日：2017-09-12

申请号：US14883610

申请日：2015-10-14

Applicant: INTEL CORPORATION

Inventor： Debaleena Das

IPC: H03M13/00 ,  G06F11/10 ,  G11C29/52 ,  G06F3/06

CPC classification number: G06F11/1068 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/1048 ,  G11C5/04 ,  G11C29/52 ,  G11C2029/0411

Abstract: Provided are an apparatus and method for generating common locator bits to locate a device or column error during error correction operation for a memory subsystem having memory modules, each including a plurality of memory devices. Error detection logic generates common locator bits from device bits in a plurality of memory devices in one of the memory modules. The error detection logic uses the common locator bits to locate a column across at least two of the memory devices having an error when there is a column error and to locate a memory device in the devices having an error when there is a device error. A same of the common locator bits are used to locate both one of the columns and the memory devices having errors. Error correction is performed on the located memory device or column having the error.

公开(公告)号：US09691505B2

公开(公告)日：2017-06-27

申请号：US14670412

申请日：2015-03-27

Applicant: Intel Corporation

Inventor： Debaleena Das ,  Rajat Agarwal

IPC: G11C29/42 ,  G06F3/06 ,  G11C29/44 ,  G11C29/52 ,  G06F11/10 ,  G11C29/04

CPC classification number: G11C29/42 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/1048 ,  G11C29/44 ,  G11C29/52 ,  G11C2029/0411

Abstract: Error correction in a memory subsystem includes determining whether an error is a transient error or a persistent error, and adjusting an approach to ECC (error checking and correction) based on error type. The type of error can be determined by a built in self-test. If the error is a persistent error, the memory controller can perform in erasure mode, including correcting an erasure for an identified error location prior to applying an ECC correction algorithm. Otherwise, if the error is transient, the memory controller can perform standard full ECC correction by applying the ECC correction algorithm.

公开(公告)号：US20160284424A1

公开(公告)日：2016-09-29

申请号：US14670412

申请日：2015-03-27

Applicant: Intel Corporation

Inventor： Debaleena Das ,  Rajat Agarwal

IPC: G11C29/42 ,  G06F3/06 ,  G06F11/10

CPC classification number: G11C29/42 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/1048 ,  G11C29/44 ,  G11C29/52 ,  G11C2029/0411

Abstract: Error correction in a memory subsystem includes determining whether an error is a transient error or a persistent error, and adjusting an approach to ECC (error checking and correction) based on error type. The type of error can be determined by a built in self-test. If the error is a persistent error, the memory controller can perform in erasure mode, including correcting an erasure for an identified error location prior to applying an ECC correction algorithm. Otherwise, if the error is transient, the memory controller can perform standard full ECC correction by applying the ECC correction algorithm.

Abstract translation: 存储器子系统中的误差校正包括确定误差是否是瞬态误差或持续性误差，以及基于误差类型调整ECC（错误检查和校正）的方法。 错误的类型可以通过内置的自检来确定。 如果错误是持续错误，则存储器控制器可以在擦除模式下执行，包括在应用ECC校正算法之前校正对所识别的错误位置的擦除。 否则，如果错误是瞬态的，则存储器控制器可以通过应用ECC校正算法执行标准的全ECC校正。

公开(公告)号：US20140229797A1

公开(公告)日：2014-08-14

申请号：US13997616

申请日：2012-03-30

Applicant: INTEL CORPORATION

Inventor： Rajat Agrawal ,  Debaleena Das ,  Kai Cheng

IPC: H03M13/05

CPC classification number: H03M13/05 ,  G06F11/1064 ,  G06F12/0895 ,  G11C2029/0411 ,  Y02D10/13

Abstract: Methods, techniques, systems and apparatuses for utilizing reserved space for error correcting functionality. A cache line (“reserved line”) in a plurality of cache lines to store error correcting code (ECC) data is utilized for storing ECC data corresponding to other cache lines within the plurality of cache lines when a memory device has failed.

Abstract translation: 用于利用预留空间进行纠错功能的方法，技术，系统和装置。 当存储器件发生故障时，用于存储纠错码（ECC）数据的多个高速缓存行中的高速缓存行（“保留行”）用于存储与多个高速缓存行中的其它高速缓存行相对应的ECC数据。