公开(公告)号：US20220156211A1

公开(公告)日：2022-05-19

申请号：US17559427

申请日：2021-12-22

Applicant: Intel Corporation

Inventor： Eng Hun Ooi ,  Su Wei Lim ,  Vaibhav Khamkar

IPC: G06F13/40 ,  G06F13/42 ,  G06F15/78 ,  G06F9/455

Abstract: Systems or methods of the present disclosure may provide a peripheral component interconnect express (PCIe) device that comprises a programmable fabric. The programmable fabric comprises multiple PCIe physical functions. The programmable fabric also includes switch circuitry having one or more embedded endpoints that dynamically hides or exposes one or more of the multiple PCIe physical functions from a bare metal mode host server without using a reset.

公开(公告)号：US11307638B2

公开(公告)日：2022-04-19

申请号：US16217204

申请日：2018-12-12

Applicant: Intel Corporation

Inventor： Ang Li ,  Kuan Hau Tan ,  Eng Hun Ooi

IPC: G06F1/00 ,  G06F1/3234 ,  G06F16/23 ,  G06F1/3287 ,  G06F1/3215 ,  G06F1/3206

Abstract: Methods, apparatus, and systems for securely providing multiple wake-up time options for PCI Express (PCIe) devices. Under one approach, Vendor Define Messages (VDMs) are exchanged between a host application layer in a host and a device application layer in a PCIe endpoint device coupled to the host via a PCIe link to effect changes to the L1.2 Substate exit time of a PCIe device. Under another approach, Vendor-Specific Extended Capability (VSEC) structures are exchanged between a host application layer and a device application layer to effect the changes. The VDMs and VSEC structures may also be used to enable a host to read Tpower_on capability information defining power modes supported by a PCIe device. Additionally, VSEC implementations are provided that implement VSEC components in the PCIe device transaction layer or the PCIe device application layer.

公开(公告)号：US10572339B2

公开(公告)日：2020-02-25

申请号：US15756039

申请日：2018-02-27

Applicant: Intel Corporation

Inventor： Robert J. Royer, Jr. ,  Blaise Fanning ,  Eng Hun Ooi

IPC: H03M13/00 ,  G06F11/10 ,  G06F12/0866 ,  G06F12/084

Abstract: Apparatus, systems, and methods to manage memory latency operations are described. In one embodiment, an electronic device comprises a processor and a memory control logic to receive data from a remote memory device, store the data in a local cache memory, receive an error correction code indicator associated with the data, and implement a data management policy in response to the error correction code indicator. Other embodiments are also disclosed and claimed.

公开(公告)号：US09952619B2

公开(公告)日：2018-04-24

申请号：US14866237

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Anoop Mukker ,  Eng Hun Ooi ,  Robert J. Royer, Jr. ,  Brian R. McFarlane

IPC: G06F1/08 ,  G06F1/12

CPC classification number: G06F1/08 ,  G06F1/12 ,  G06F13/40 ,  G06F13/4291 ,  H04J3/0697

Abstract: The present disclosure provides devices and techniques to dynamically change the operating frequency of an interface where components on the interface have non-common clocks. An interface component may be provided with a frequency negotiation component to negotiate a shift in an operating frequency with other component on an interface where the different components have non-common clocks.

公开(公告)号：US09904592B2

公开(公告)日：2018-02-27

申请号：US14775848

申请日：2014-02-26

Applicant: Intel Corporation

Inventor： Robert J. Royer, Jr. ,  Blaise Fanning ,  Eng Hun Ooi

IPC: G11C29/00 ,  G06F11/10 ,  G06F12/0866 ,  G06F12/084

CPC classification number: G06F11/1064 ,  G06F11/1048 ,  G06F12/084 ,  G06F12/0866 ,  G06F2212/1032 ,  G06F2212/313

Abstract: Apparatus, systems, and methods to manage memory latency operations are described. In one embodiment, an electronic device comprises a processor and a memory control logic to receive data from a remote memory device, store the data in a local cache memory, receive an error correction code indicator associated with the data, and implement a data management policy in response to the error correction code indicator. Other embodiments are also disclosed and claimed.

公开(公告)号：US09792246B2

公开(公告)日：2017-10-17

申请号：US14583623

申请日：2014-12-27

Applicant: Intel Corporation

Inventor： Ee Loon Teoh ,  Eng Hun Ooi ,  Christopher P Mozak ,  Brian R McFarlane

IPC: G06F13/42 ,  G06F13/28

CPC classification number: G06F13/4282 ,  G06F13/1668 ,  G06F13/28 ,  G06F21/79 ,  Y02D10/14 ,  Y02D10/151

Abstract: An I/O interface supports scrambling, where the scrambling can include nonlinear scrambling of the scrambling code, or dynamic bus inversion of the scrambling code, or selective switching of selected bits of the scrambling code, or a combination of these. The transmitting device includes a scrambler and the receiving device includes a descrambler. Both the scrambler and the descrambler generate a linear feedback scrambling code modified by applying one or more of the techniques mentioned above. The modified scrambling code may cause fewer than half of the scrambled output bits to be toggled with respect to a previous scrambled output. The scrambler applies the modified scrambling code to a signal to transmit. The descrambler applies the modified scrambling code to a received signal.

公开(公告)号：US20170212832A1

公开(公告)日：2017-07-27

申请号：US15396732

申请日：2017-01-02

Applicant: Intel Corporation

Inventor： Eng Hun Ooi ,  Robert J. Royer ,  Michael W. Williams ,  Jeffrey R. Wilcox ,  Ritesh B. Trivedi ,  Blaise Fanning

IPC: G06F12/02 ,  G06F3/06 ,  G06F13/42 ,  G06F13/12 ,  G06F13/16 ,  G06F13/38

CPC classification number: G06F12/0246 ,  G06F3/0679 ,  G06F12/02 ,  G06F13/12 ,  G06F13/16 ,  G06F13/1668 ,  G06F13/38 ,  G06F13/4234 ,  G06F2212/7202

Abstract: In an embodiment, a memory interface may send an indication that a request is being sent. The indication may be sent to a non-volatile memory via a point-to-point bus between a memory interface and the non-volatile memory. The memory interface may send the request to the non-volatile memory via the bus. The request may include an address that may be used to identify a location for storing or reading data. The non-volatile memory may acquire the request from the bus and process the request. After processing the request, the non-volatile memory may send an indication to the memory interface that indicates the non-volatile memory has a response to send to the memory interface. The memory interface may grant access to the bus to the non-volatile memory. After being granted access to the bus, the non-volatile memory may send the response to the memory interface.

公开(公告)号：US11387852B2

公开(公告)日：2022-07-12

申请号：US16639780

申请日：2018-09-17

Applicant: Intel Corporation

Inventor： Elan Banin ,  Eytan Mann ,  Rotem Banin ,  Ronen Gernizky ,  Ofir Degani ,  Igal Kushnir ,  Shahar Porat ,  Amir Rubin ,  Vladimir Volokitin ,  Elinor Kashani ,  Dmitry Felsenstein ,  Ayal Eshkoli ,  Tai Davidson ,  Eng Hun Ooi ,  Yossi Tsfati ,  Ran Shimon

IPC: H04B1/04 ,  H04L7/033

Abstract: An apparatus for generating a data signal comprises a processing circuit configured to generate the data signal, the data signal comprising a sequence of a first signal edge of a first type, a second signal edge of a second type, and a third signal edge of the first type, the first signal edge and the second signal edge being separated by a first time period corresponding to first data to be transmitted, and the second signal edge and the third signal edge being separated by a second time period corresponding to second data to be transmitted. An output interface circuit is configured to output the data signal.

公开(公告)号：US20220197519A1

公开(公告)日：2022-06-23

申请号：US17128072

申请日：2020-12-19

Applicant: Intel Corporation

Inventor： Chia-Hung Kuo ,  Anoop Mukker ,  Eng Hun Ooi ,  Avishay Snir ,  Shrinivas Venkatraman ,  Kuan Hua Tan ,  Wai Ben Lin

IPC: G06F3/06

Abstract: A multi-level memory architecture scheme to dynamically balance a number of parameters such as power, thermals, cost, latency and performance for memory levels that are progressively further away from the processor in the platform based on how applications are using memory levels that are further away from processor cores. In some examples, the decision making for the state of the far memory (FM) is decentralized. For example, a processor power management unit (p-unit), near memory controller (NMC), and/or far memory host controller (FMHC) makes decisions about the power and/or performance state of the FM at their respective levels. These decisions are coordinated to provide the most optimum power and/or performance state of the FM for a given time. The power and/or performance state of the memories adaptively change to changing workloads and other parameters even when the processor(s) is in a particular power state.

公开(公告)号：US11080223B2

公开(公告)日：2021-08-03

申请号：US16513941

申请日：2019-07-17

Applicant: Intel Corporation

Inventor： Kuan Hua Tan ,  Eng Hun Ooi ,  Ang Li

IPC: G06F13/42 ,  G06F9/445

Abstract: A device connected by a link to a host system can include a first port to receive a capability configuration message across a link and a message request receiving logic comprising hardware circuitry to identify a capability of the device identified in the capability configuration message, determine that the capability is to be presented or hidden from operation based on a capability hide enable bit in the capability configuration message, and configure a capability linked list to present or hide the capability based on the determination. The device can also include a message response generator logic comprising hardware circuitry to generate a response message indicating that the capability is to be presented or hidden from operation. The device can include a second port to transmit the response message across the link.