公开(公告)号：US20200320776A1

公开(公告)日：2020-10-08

申请号：US16746636

申请日：2020-01-17

Applicant: INTEL CORPORATION

Inventor： MICHAEL DOYLE ,  KARTHIK VAIDYANATHAN

IPC: G06T15/10 ,  G06T9/00 ,  G06T1/60 ,  G06T15/06

Abstract: Apparatus and method for efficient BVH construction. For example, one embodiment of an apparatus comprises: a memory to store graphics data for a scene including a plurality of primitives in a scene at a first precision; a geometry quantizer to read vertices of the primitives at the first precision and to adaptively quantize the vertices of the primitives to a second precision associated with a first local coordinate grid of a first BVH node positioned within a global coordinate grid, the second precision lower than the first precision; a BVH builder to determine coordinates of child nodes of the first BVH node by performing non-spatial-split binning or spatial-split binning for the first BVH node using primitives associated with the first BVH node, the BVH builder to determine final coordinates for the child nodes based, at least in part, on an evaluation of surface areas of different bounding boxes generated for each of the child node.

公开(公告)号：US20200211263A1

公开(公告)日：2020-07-02

申请号：US16235906

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： SCOTT JANUS ,  PRASOONKUMAR SURTI ,  KARTHIK VAIDYANATHAN ,  ALEXEY SUPIKOV ,  GABOR LIKTOR ,  CARSTEN BENTHIN ,  PHILIP LAWS ,  MICHAEL DOYLE

IPC: G06T15/06 ,  G06T17/00 ,  G06T15/00 ,  G06T1/60

Abstract: Apparatus and method for a hierarchical beam tracer. For example, one embodiment of an apparatus comprises: a beam generator to generate beam data associated with a beam projected into a graphics scene; a bounding volume hierarchy (BVH) generator to generate BVH data comprising a plurality of hierarchically arranged BVH nodes; a hierarchical beam-based traversal unit to determine whether the beam intersects a current BVH node and, if so, to responsively subdivide the beam into N child beams to test against the current BVH node and/or to traverse further down the BVH hierarchy to select a new BVH node, wherein the hierarchical beam-based traversal unit is to iteratively subdivide successive intersecting child beams and/or to continue to traverse down the BVH hierarchy until a leaf node is reached with which at least one final child beam is determined to intersect; the hierarchical beam-based traversal unit to generate a plurality of rays within the final child beam; and intersection hardware logic to perform intersection testing for any rays intersecting the leaf node, the intersection testing to determine intersections between the rays intersecting the leaf node and primitives bounded by the leaf node.

公开(公告)号：US20200211262A1

公开(公告)日：2020-07-02

申请号：US16235838

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： KARTHIK VAIDYANATHAN ,  MICHAEL APODACA ,  THOMAS RAOUX ,  CARSTEN BENTHIN ,  KAI XIAO ,  CARSON BROWNLEE ,  JOSHUA BARCZAK

IPC: G06T15/06 ,  G06T1/60

Abstract: An apparatus and method to execute ray tracing instructions. For example, one embodiment of an apparatus comprises execution circuitry to execute a dequantize instruction to convert a plurality of quantized data values to a plurality of dequantized data values, the dequantize instruction including a first source operand to identify a plurality of packed quantized data values in a source register and a destination operand to identify a destination register in which to store a plurality of packed dequantized data values, wherein the execution circuitry is to convert each packed quantized data value in the source register to a floating point value, to multiply the floating point value by a first value to generate a first product and to add the first product to a second value to generate a dequantized data value, and to store the dequantized data value in a packed data element location in the destination register.

公开(公告)号：US20200211253A1

公开(公告)日：2020-07-02

申请号：US16236176

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： GABOR LIKTOR ,  KARTHIK VAIDYANATHAN ,  JEFFERSON AMSTUTZ ,  ATSUO KUWAHARA ,  MICHAEL DOYLE ,  TRAVIS SCHLUESSLER

IPC: G06T15/00 ,  G06T15/06 ,  G06T1/60

Abstract: Apparatus and method for speculative execution of hit and intersection shaders on programmable ray tracing architectures. For example, one embodiment of an apparatus comprises: single-instruction multiple-data (SIMD) or single-instruction multiple-thread (SIMT) execution units (EUs) to execute shaders; and ray tracing circuitry to execute a ray traversal thread, the ray tracing engine comprising: traversal/intersection circuitry, responsive to the traversal thread, to traverse a ray through an acceleration data structure comprising a plurality of hierarchically arranged nodes and to intersect the ray with a primitive contained within at least one of the nodes; and shader deferral circuitry to defer and aggregate multiple shader invocations resulting from the traversal thread until a particular triggering event is detected, wherein the multiple shaders are to be dispatched on the EUs in a single shader batch upon detection of the triggering event.

公开(公告)号：US20200211151A1

公开(公告)日：2020-07-02

申请号：US16235604

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： KARTHIK VAIDYANATHAN ,  SVEN WOOP ,  CARSTEN BENTHIN

IPC: G06T1/60 ,  G06T15/06 ,  G06T17/00

Abstract: Apparatus and method for a compressed stack representation for a BVH. For example, one embodiment of an apparatus comprises: a ray generator to generate a plurality of rays in a first graphics scene; a bounding volume hierarchy (BVH) generator to construct a BVH comprising a plurality of hierarchically arranged nodes, wherein the BVH comprises a specified number of child nodes at a current BVH level beneath a parent node in the hierarchy; traversal/intersection circuitry to traverse one or more of the rays through the hierarchically arranged nodes of the BVH and intersect the one or more rays with primitives contained within the nodes; a short traversal stack of a fixed size comprising a specified number of entries fewer than the number of child nodes beneath the parent node, each entry associated with a child node at the current BVH level, the entries ordered from top to bottom within the short traversal stack based on a sorted distance of each respective child node, wherein each entry includes a field to indicate whether that entry is associated with a final child in the current BVH level; wherein the traversal/intersection circuitry is to process entries from the top of the traversal stack, removing entries as they are processed, the traversal/intersection circuitry to determine that a current entry is associated with the final child node at the current BVH level by reading a first value in the field.

公开(公告)号：US20200043218A1

公开(公告)日：2020-02-06

申请号：US16056222

申请日：2018-08-06

Applicant: Intel Corporation

Inventor： KARTHIK VAIDYANATHAN ,  WON-JONG LEE ,  GABOR LIKTOR ,  JOHN G. GIERACH ,  PAWEL MAJEWSKI ,  PRASOONKUMAR SURTI ,  CARSTEN BENTHIN ,  Sven WOOP ,  THOMAS RAOUX

IPC: G06T15/00 ,  G06T15/06 ,  G06T15/80

Abstract: Apparatus and method for programmable ray tracing with hardware acceleration on a graphics processor. For example, one embodiment of a graphics processor comprises shader execution circuitry to execute a plurality of programmable ray tracing shaders. The shader execution circuitry includes a plurality of single instruction multiple data (SIMD) execution units. Sorting circuitry regroups data associated with one or more of the programmable ray tracing shaders to increase occupancy for SIMD operations performed by the SIMD execution units; and fixed-function intersection circuitry coupled to the shader execution circuitry detects intersections between rays and bounding volume hierarchies (BVHs) and/or objects contained therein and to provide results indicating the intersections to the sorting circuitry.