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公开(公告)号：US10162616B2
公开(公告)日：2018-12-25
申请号：US14752440
申请日：2015-06-26
Applicant: Intel Corporation
Inventor： Tugrul Ince , Koichi Yamada
Abstract: The present disclosure is directed to a system for binary translation version protection. Activity occurring in a device that may potentially cause native code to be altered may cause the device to prevent binary translations corresponding to the native code from being executed until a determination is made as to whether the binary translation needs to be regenerated. The native code may be stored in a memory page having an access permission that does not permit writes. Attempts to alter the native code would require the access permission of the memory page to be set to writable, which may cause a binary translation (BT) module to be notified of the potential change. The BT module may mark any binary translations corresponding to the native code as stale, and may cause a page permission control module to update memory pages including the binary translations to have an access permission of non-executable.
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12.发明授权公开(公告)号：US09477453B1
公开(公告)日：2016-10-25
申请号：US14748363
申请日：2015-06-24
Applicant: Intel Corporation
Inventor： Tugrul Ince , Koichi Yamada , Paul Caprioli , Jiwei Lu
CPC classification number: G06F8/52 , G06F9/4486 , G06F12/08 , G06F2212/451
Abstract: Technologies for shadow stack management include a computing device that, when executing a translated call routine in a translated binary, pushes a native return address on to a native stack of the computing device, adds a constant offset to a stack pointer of the computing device, executes a native call instruction to a translated call target, and, after executing the native call instruction, subtracts the constant offset from the stack pointer. Executing the native call instruction pushes a translated return address onto a shadow stack of the computing device. The computing device may map two or more virtual memory pages of the shadow stack onto a single physical memory page. The computing device may execute a translated return routine that pops the native return address from the native stack, adds the constant offset to the stack pointer, and executes a native return instruction. Other embodiments are described and claimed.
Abstract translation: 用于阴影堆栈管理的技术包括计算设备，当在翻译的二进制文件中执行转换的调用例程时，将本地返回地址推送到计算设备的本机堆栈，向计算设备的堆栈指针添加恒定偏移量， 对转换后的呼叫目标执行本机调用指令，执行本地调用指令后，从堆栈指针中减去常量偏移量。 执行本地调用指令将转换后的返回地址推送到计算设备的影子栈上。 计算设备可以将阴影栈的两个或多个虚拟存储器页面映射到单个物理存储器页面上。 计算设备可以执行翻译的返回例程，其从本机堆栈弹出本地返回地址，将常量偏移量添加到堆栈指针，并执行本地返回指令。 描述和要求保护其他实施例。
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13.发明申请公开(公告)号：US20160216973A9
公开(公告)日：2016-07-28
申请号：US13956495
申请日：2013-08-01
Applicant: Intel Corporation
Inventor： Koichi Yamada , GAD SHEAFFER , JAN GRAY , LANDY WANG , MARTIN TAILLEFER , ARUN KISHAN , ALI-REZA ADL-TABATABAI , DAVID CALLAHAN
IPC: G06F9/38
CPC classification number: G06F9/467 , G06F9/30076 , G06F9/3834 , G06F9/3836 , G06F9/3857 , G06F9/3861
Abstract: In one embodiment, the present invention includes a method for receiving control in a kernel mode via a ring transition from a user thread during execution of an unbounded transactional memory (UTM) transaction, updating a state of a transaction status register (TSR) associated with the user thread and storing the TSR with a context of the user thread, and later restoring the context during a transition from the kernel mode to the user thread. In this way, the UTM transaction may continue on resumption of the user thread. Other embodiments are described and claimed.
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公开(公告)号：US11507412B2
公开(公告)日：2022-11-22
申请号：US16861082
申请日：2020-04-28
Applicant: Intel Corporation
Inventor： Keqiang Wu , Jiwei Lu , Koichi Yamada , Yong-Fong Lee
IPC: G06F9/46
Abstract: A disclosed example apparatus includes memory; and processor circuitry to: identify a lock-protected section of instructions in the memory; replace lock/unlock instructions with transactional lock acquire and transactional lock release instructions to form a transactional process; and execute the transactional process in a speculative execution.
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公开(公告)号：US10789056B2
公开(公告)日：2020-09-29
申请号：US15202745
申请日：2016-07-06
Applicant: Intel Corporation
Inventor： Koichi Yamada , Jose A. Baiocchi Paredes , Abhik Sarkar , Ajay Harikumar , Jiwei Lu
Abstract: Technologies for binary translation include a computing device that allocates a translation cache shared by all threads associated with a corresponding execution domain. The computing device assigns a thread to an execution domain, translates original binary code of the thread to generate translated binary code, and installs the translated binary code into the corresponding translation cache for execution. The computing device may allocate a global region cache, generate region metadata associated with the original binary code of a thread, and store the region metadata in the global region cache. The original binary code may be translated using the region metadata. The computing device may allocate a global prototype cache, translate the original binary code of a thread to generate prototype code, and install the prototype code in the global prototype cache. The prototype code may be a non-executable version of the translated binary code. Other embodiments are described and claimed.
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Patent Agency Ranking
公开(公告)号：US10649746B2
公开(公告)日：2020-05-12
申请号：US15237443
申请日：2016-08-15
Applicant: Intel Corporation
Inventor： Abhay S. Kanhere , Paul Caprioli , Koichi Yamada , Suriya Madras-Subramanian , Srinivas Suresh
Abstract: A micro-architecture may provide a hardware and software co-designed dynamic binary translation. The micro-architecture may invoke a method to perform a dynamic binary translation. The method may comprise executing original software code compiled targeting a first instruction set, using processor hardware to detect a hot spot in the software code and passing control to a binary translation translator, determining a hot spot region for translation, generating the translated code using a second instruction set, placing the translated code in a translation cache, executing the translated code from the translated cache, and transitioning back to the original software code after the translated code finishes execution.
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17.发明授权公开(公告)号：US10395033B2
公开(公告)日：2019-08-27
申请号：US15281825
申请日：2016-09-30
Applicant: Intel Corporation
Inventor： Tugrul Ince , Koichi Yamada , Ajay Harikumar , Alex Nayshtut
Abstract: In one embodiment, a binary translator to perform binary translation of code is to: perform a first binary analysis of a first code block to determine whether a second control transfer instruction is included in the first code block, where the first code block includes a return target of a first control transfer instruction; perform a second binary analysis of a second code block to determine whether the second code block includes the first control transfer instruction, where the second code block includes a call target of the second control transfer instruction; and store an address pair associated with the first control transfer instruction in a whitelist if the second control transfer instruction is included in the first code block and the first control transfer instruction is included in the second code block. Other embodiments are described and claimed.
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公开(公告)号：US10055585B2
公开(公告)日：2018-08-21
申请号：US14129246
申请日：2013-08-28
Applicant: INTEL CORPORATION
Inventor： Greg William Dalcher , Ravi L. Sahita , Palanivelra Shanmugavelayutham , Koichi Yamada , Arvind Krishnaswamy
CPC classification number: G06F21/566 , G06F21/554
Abstract: Technologies for assembling an execution profile of an event are disclosed. The technologies may include monitoring the event for a branch instruction, generating a callback to a security module upon execution of the branch instruction, filtering the callback according to a plurality of event identifiers, and validating a code segment associated with the branch instruction, the code segment including code executed before the branch instruction and code executed after the branch instruction.
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公开(公告)号：US20170212825A1
公开(公告)日：2017-07-27
申请号：US15403120
申请日：2017-01-10
Applicant: Intel Corporation
Inventor： Paul Caprioli , Matthew C. Merten , Muawya M. Al-Otoom , Omar M. Shaikh , Abhay S. Kanhere , Suresh Srinivas , Koichi Yamada , Vivek Thakkar , Pawel Osciak
CPC classification number: G06F11/3466 , G06F8/40 , G06F8/52 , G06F9/3017 , G06F9/3842 , G06F9/4552 , G06F11/073 , G06F11/3616 , G06F11/3652
Abstract: A hardware profiling mechanism implemented by performance monitoring hardware enables page level automatic binary translation. The hardware during runtime identifies a code page in memory containing potentially optimizable instructions. The hardware requests allocation of a new page in memory associated with the code page, where the new page contains a collection of counters and each of the counters corresponds to one of the instructions in the code page. When the hardware detects a branch instruction having a branch target within the code page, it increments one of the counters that has the same position in the new page as the branch target in the code page. The execution of the code page is repeated and the counters are incremented when branch targets fall within the code page. The hardware then provides the counter values in the new page to a binary translator for binary translation.
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20.发明授权公开(公告)号：US09569613B2
公开(公告)日：2017-02-14
申请号：US14581871
申请日：2014-12-23
Applicant: INTEL CORPORATION
Inventor： Koichi Yamada , Palanivelrajan Shanmugavelayutham , Sravani Konda
CPC classification number: G06F21/54 , G06F8/30 , G06F8/52 , G06F9/4552
Abstract: Various embodiments are generally directed to an apparatus, method and other techniques to determine a valid target address for a branch instruction from information stored in a relocation table, a linkage table, or both, the relocation table and the linkage table associated with a binary file and store the valid target address in a table in memory, the valid target address to validate a target address for a translated portion of a routine of the binary file.
Abstract translation: 各种实施例通常涉及一种装置，方法和其他技术，以从存储在重定位表，链接表或二者中的信息确定分支指令的有效目标地址，重定位表和与二进制文件相关联的链接表 并将有效目标地址存储在存储器中的表中，该有效目标地址用于验证二进制文件的例程的翻译部分的目标地址。
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