公开(公告)号：US20210089448A1

公开(公告)日：2021-03-25

申请号：US16576687

申请日：2019-09-19

Applicant: Intel Corporation

Inventor： Huichu Liu ,  Tanay Karnik ,  Tejpal Singh ,  Yen-Cheng Liu ,  Lavanya Subramanian ,  Mahesh Kumashikar ,  Sri Harsha Chodav ,  Sreenivas Subramoney ,  Kaushik Vaidyanathan ,  Daniel H. Morris ,  Uygar E. Avci ,  Ian A. Young

IPC: G06F12/0804 ,  G06F11/20 ,  G06F12/0806 ,  G06F12/0866

Abstract: Described is an low overhead method and apparatus to reconfigure a pair of buffered interconnect links to operate in one of these three modes—first mode (e.g., bandwidth mode), second mode (e.g., latency mode), and third mode (e.g., energy mode). In bandwidth mode, each link in the pair buffered interconnect links carries a unique signal from source to destination. In latency mode, both links in the pair carry the same signal from source to destination, where one link in the pair is “primary” and other is called the “assist”. Temporal alignment of transitions in this pair of buffered interconnects reduces the effective capacitance of primary, thereby reducing delay or latency. In energy mode, one link in the pair, the primary, alone carries a signal, while the other link in the pair is idle. An idle neighbor on one side reduces energy consumption of the primary.

公开(公告)号：US09698781B1

公开(公告)日：2017-07-04

申请号：US15165501

申请日：2016-05-26

Applicant: INTEL CORPORATION

Inventor： Arojit Roychowdhury ,  Ajaya Durg ,  Shilpa Huddar ,  Sunil Shanbhag ,  Vishram Sarurkar ,  Tejpal Singh

IPC: H03K19/00

CPC classification number: H03K19/0016

Abstract: An electronic apparatus may be provided that includes a clock device to provide a clock signal, and a clock gate to receive the clock signal, the clock gate to be selectively provided in an enabled state or a disabled state. The electronic apparatus may also include a controller to determine a frequency transition and to control the clock gate to be in the enabled state or the disabled state based on the determined frequency transition.

公开(公告)号：US20170019350A1

公开(公告)日：2017-01-19

申请号：US14800552

申请日：2015-07-15

Applicant: INTEL CORPORATION

Inventor： Bahaa Fahim ,  Yen-Cheng Liu ,  Chung-Chi Wang ,  Donald C. Soltis, JR. ,  Terry C. Huang ,  Tejpal Singh ,  Bongjin Jung ,  Nazar Syed Haider

IPC: H04L12/933 ,  H04L12/937

CPC classification number: H04L49/103 ,  G06F11/1064 ,  G06F13/4022 ,  H04L49/254

Abstract: A shared mesh comprises a mesh station. The mesh station is used to couple to at least a first core component and a second core component. The mesh station includes a logic unit. The mesh station is shared by at least the first core component and the second core component. A memory is coupled to the mesh station.

Abstract translation: 共享网格包括网格站。 网状站用于耦合到至少第一核心组件和第二核心组件。 网格站包括一个逻辑单元。 网状站由至少第一核心组件和第二核心组件共享。 存储器耦合到网格站。