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    Memory bus MR register programming process
    11.
    发明授权
    Memory bus MR register programming process 有权

    公开(公告)号：US10380043B2

    公开(公告)日：2019-08-13

    申请号：US15718346

    申请日：2017-09-28

    Applicant: Intel Corporation

    Inventor： Tonia G. Morris ,  John V. Lovelace ,  John R. Goles

    IPC: G06F13/36 ,  G06F13/16 ,  G06F1/10

    Abstract: A method performed by a memory chip is described. The method includes receiving an activated chip select signal. The method also includes receiving, with the chip select signal being activated, a command code on a command/address (CA) bus that identifies a next portion of an identifier for the memory chip. The method also includes receiving the next portion of the identifier on a portion of the memory chip's data inputs. The method also includes repeating the receiving of the activated chip select signal, the command code and the next portion until the entire identifier has been received and storing the entire identifier in a register.

    Training for chip select signal read operations by memory devices
    12.
    发明授权
    Training for chip select signal read operations by memory devices 有权

    公开(公告)号：US12009023B2

    公开(公告)日：2024-06-11

    申请号：US17441667

    申请日：2019-05-24

    Applicant: Intel Corporation

    Inventor： Zhenglong Wu ,  Tonia G. Morris ,  Christina Jue ,  Daniel Becerra Perez ,  David G. Ellis

    IPC: G11C11/4076 ,  G11C11/4096

    CPC classification number: G11C11/4076 ,  G11C11/4096

    Abstract: A reference voltage value and a chip select (CS) signal timing delay provided to memory devices can be determined based on samples of the CS signal received by the memory devices. The CS signal can be provided to the memory devices with varying time delays and for various reference voltages. Various samples of the CS signal from the memory devices can indicate different times for rising and falling edges of the CS signal. A composite signal eye can be generated by the latest occurring rising edge and the earliest occurring falling edge of the CS signal. The reference voltage value and timing delay can be chosen based on the composite signal eye width that is the closest to a reference eye width.

    Registering clock driver controlled decision feedback equalizer training process
    13.
    发明授权
    Registering clock driver controlled decision feedback equalizer training process 有权

    公开(公告)号：US11360874B2

    公开(公告)日：2022-06-14

    申请号：US16919649

    申请日：2020-07-02

    Applicant: Intel Corporation

    Inventor： Tonia G. Morris

    IPC: G11C7/22 ,  G06F11/34 ,  G06F11/30 ,  G11C29/02

    Abstract: A method is described. The method includes receiving from a memory controller configuration information for a testing sequence and storing the configuration information in configuration register space of the driver circuit. The method also includes controlling the next testing sequence. The testing sequence includes sweeping values of a tap coefficient of a DFE circuit of the driver circuit and sweeping a voltage of a slicer of the driver circuit. The method includes sending results of the testing sequence to the memory controller. The results are to determine a value for the DFE tap coefficient.

    Efficiently training memory device chip select control
    14.
    发明授权
    Efficiently training memory device chip select control 有权

    公开(公告)号：US11061590B2

    公开(公告)日：2021-07-13

    申请号：US16547197

    申请日：2019-08-21

    Applicant: Intel Corporation

    Inventor： Tonia G. Morris ,  Christopher P. Mozak ,  Christopher E. Cox

    IPC: G06F3/06 ,  G11C11/4076 ,  G11C8/12 ,  G11C29/00 ,  G11C29/02

    Abstract: A chip select training mode (CSTM) enables a memory subsystem to train a chip select signal separately from command bus training. A memory device and a memory controller can connect via a command bus including a chip select signal line. Instead of training the chip select along with other signal lines of the command bus, a CSTM mode enables the memory subsystem to more accurately train the chip select. The memory device can be triggered for CSTM mode with a command, and then train voltage margining for the CS signal line to align chip select signaling with the memory subsystem clock signal.

    DEVICE, SYSTEM AND METHOD TO GENERATE LINK TRAINING SIGNALS
    15.
    发明申请
    DEVICE, SYSTEM AND METHOD TO GENERATE LINK TRAINING SIGNALS 审中-公开

    公开(公告)号：US20200042209A1

    公开(公告)日：2020-02-06

    申请号：US16390551

    申请日：2019-04-22

    Applicant: Intel Corporation

    Inventor： Tonia G. Morris ,  Moshe Jacob Finkelstein ,  Ramesh Subashchandrabose ,  Lohit R. Yerva

    IPC: G06F3/06 ,  G06N20/00

    Abstract: Techniques and mechanisms for providing communications which facilitate link training. In an embodiment, a memory controller includes, or couples to, trainer circuitry which is configured to provide instructions to generate memory access commands. The instructions are accessed at the circuitry in response to an indication that link training is performed, where the accessing is independent of communication with a processor coupled to the memory controller. Based on the instructions, memory access commands are communicated via a link between the memory controller and a memory device. Link training is performed based on an evaluation of one or more characteristics of the link communications. In another embodiment, memory access commands are generated, based on the instructions, while a validity of data at the memory device is maintained.

    Read training a memory controller
    17.
    发明授权
    Read training a memory controller 有权
    阅读培训内存控制器

    公开(公告)号：US09058111B2

    公开(公告)日：2015-06-16

    申请号：US14581011

    申请日：2014-12-23

    Applicant: INTEL CORPORATION

    Inventor： Tonia G. Morris ,  Jonathan C. Jasper ,  Arnaud J. Forestier

    IPC: G06F3/06 ,  G06F3/00 ,  G06F13/38

    CPC classification number: G06F13/1668 ,  G06F3/061 ,  G06F3/0632 ,  G06F3/0673 ,  G06F13/1689 ,  G06F13/4068 ,  G06F13/4234 ,  G11C11/4093 ,  G11C11/4096

    Abstract: Provided are a device and computer readable storage medium for programming a memory module to initiate a training mode in which the memory module transmits continuous bit patterns on a side band lane of the bus interface; receiving the bit patterns over the bus interface; determining from the received bit patterns a transition of values in the bit pattern to determine a data eye between the determined transitions of the values; and determining a setting to control a phase interpolator to generate interpolated signals used to sample data within the determined data eye.

    Abstract translation: 提供了一种用于对存储器模块进行编程以启动训练模式的装置和计算机可读存储介质，其中存储器模块在总线接口的边带通道上发送连续位模式; 通过总线接口接收位模式; 从接收到的位模式确定位模式中的值的转变以确定所确定的值的转换之间的数据眼; 以及确定设置以控制相位内插器以产生用于对所确定的数据眼睛内的数据进行采样的内插信号。

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