公开(公告)号：US20170187284A1

公开(公告)日：2017-06-29

申请号：US14757802

申请日：2015-12-23

Applicant: Intel Corporation

Inventor： Vaibhav Vaidya ,  Pavan Kumar ,  Krishnan Ravichandran ,  Vivek K. De

IPC: H02M3/158

CPC classification number: H02M1/083 ,  H02M1/38 ,  H02M3/1588 ,  Y02B70/1466

Abstract: Generally, this disclosure describes an apparatus. The apparatus includes switch controller circuitry. The switch controller circuitry includes dead time logic circuitry to determine an estimated dead time interval between a turn off of a first switch and a turn on of a second switch. The first switch and the second switch are coupled at a switched node. The estimated dead time interval is determined based, at least in part, on a difference between an input voltage, Vin, and a switched voltage, Vsw, detected at the switched node just prior to turning off the first switch, a parasitic capacitance, Cpar, associated with the switched node and a maximum inductor current, IL,max. The difference between Vin and Vsw represents the maximum inductor current.

公开(公告)号：US10897364B2

公开(公告)日：2021-01-19

申请号：US15846045

申请日：2017-12-18

Applicant: Intel Corporation

Inventor： Vivek De ,  Krishnan Ravichandran ,  Harish Krishnamurthy ,  Khondker Ahmed ,  Sriram Vangal ,  Vaibhav Vaidya ,  Turbo Majumder ,  Christopher Schaef ,  Suhwan Kim ,  Xiaosen Liu ,  Nachiket Desai

IPC: H04L9/32

Abstract: Spin Hall Effect (SHE) magneto junction memory cells (e.g., magnetic tunneling junction (MTJ) or spin valve based memory cells) are used to implement high entropy physically unclonable function (PUF) arrays utilizing stochastics interactions of both parameter variations of the SHE-MTJ structures as well as random thermal noises. An apparatus is provided which comprises: an array of PUF devices, wherein an individual device of the array comprises a magnetic junction and an interconnect, wherein the interconnect comprises a spin orbit coupling material; a circuitry to sense values stored in the array, and to provide an output; and a comparator to compare the output with a code.

公开(公告)号：US10205084B2

公开(公告)日：2019-02-12

申请号：US15087613

申请日：2016-03-31

Applicant: Intel Corporation

Inventor： Vaibhav Vaidya ,  Suhwan Kim

IPC: H02J7/00 ,  H01L41/113 ,  H02N2/18 ,  H02J7/34

Abstract: Techniques for harvesting electrical energy from a plurality of harvesters is disclosed. An example energy harvesting system includes a plurality of harvesters and a signal conditioning circuit selectively coupled to an output of each of the plurality of harvesters. The system also includes an energy storage element coupled to the output of the signal conditioning circuit to be charged by the plurality of harvesters through the signal conditioning circuit. The system also includes a controller to discharge a selected harvester to the signal conditioning circuit when an output of the selected harvester triggers a charge collection.

公开(公告)号：US09819266B2

公开(公告)日：2017-11-14

申请号：US14757732

申请日：2015-12-23

Applicant: Intel Corporation

Inventor： Vaibhav Vaidya ,  Vivek K. De ,  Krishnan Ravichandran

IPC: H02M3/158

CPC classification number: H02M3/158 ,  H02M1/083 ,  H02M3/1588 ,  Y02B70/1466

Abstract: Generally, this disclosure describes an apparatus. The apparatus includes switch controller circuitry and zero crossing logic circuitry. The switch controller circuitry is to control a conduction state of a high side switch and a low side switch in a DC to DC converter. The zero crossing logic circuitry includes phase comparator circuitry, a first clocking circuitry and a second clocking circuitry. Each clocking circuitry includes one or more delay elements. The zero crossing logic circuitry is to monitor a switch node voltage, Vsw, and to determine whether Vsw is greater than a reference, Vref. The switch controller circuitry is to turn off a low side switch if Vsw is greater than Vref while the low side switch is turned on, Vsw greater than Vref corresponding to a negative inductor current.

公开(公告)号：US20170187187A1

公开(公告)日：2017-06-29

申请号：US14998328

申请日：2015-12-23

Applicant: Intel Corporation

Inventor： Sally Amin ,  Sergio Carlo ,  Harish Krishnamurthy ,  Christopher Schaef ,  Vaibhav Vaidya

IPC: H02J3/38 ,  H02J7/00

Abstract: A power regulator includes a plurality of harvester switches, each coupled to receive a separate energy source, a plurality of load switches, each coupled to supply power to a separate load, an inductor to store energy received from one or more energy sources and release the energy to supply the power to one or more loads and a controller to control charging of the inductor via activation of one or more of the harvester switches and discharging of the inductor via activation of one or more of the load switches.

公开(公告)号：US20170093270A1

公开(公告)日：2017-03-30

申请号：US14866662

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： George E. Matthew ,  Rinkle Jain ,  Vaibhav Vaidya

IPC: H02M1/088 ,  G06F1/26

CPC classification number: G06F1/28 ,  G05F1/10 ,  G05F1/32 ,  G05F1/40 ,  G05F3/08 ,  G06F1/26 ,  G06F1/305 ,  H02M1/088 ,  H02M3/07 ,  H02M3/156 ,  H02M2001/0003

Abstract: Methods and apparatus relating to a low ripple mechanism of mode change in switched capacitor voltage regulators are described. In an embodiment, a mode change of a Switching Capacitor Voltage Regulator (SCVR) is caused based at least in part on a comparison of an output voltage of the SCVR and a reference voltage. The output voltage is sensed based at least in part on a clock signal. Other embodiments are also disclosed and claimed.

公开(公告)号：US20160181829A1

公开(公告)日：2016-06-23

申请号：US14580825

申请日：2014-12-23

Applicant: INTEL CORPORATION

Inventor： Lilly Huang ,  Suvankar Biswas ,  Vaibhav Vaidya ,  Krishnan RAVICHANDRAN

IPC: H02J7/00

CPC classification number: H02J7/007 ,  H01M10/44 ,  H01M10/465 ,  H02J7/0077 ,  H02J7/022 ,  H02J7/04

Abstract: In embodiments, apparatuses, methods and systems associated with battery charging are disclosed herein. In various embodiments, a reference current selector may receive a battery voltage sense input and output a reference current level signal, a power point check detector may receive a power supply sense input and output a power point check signal, and a controller coupled to the reference current selector and the power point check detector may receive a battery current sense input and switch a control output based at least in part on the reference current level signal, the battery current sense input, and the power point check signal. Other embodiments may be described and/or claimed.

Abstract translation: 在实施例中，本文公开了与电池充电相关联的装置，方法和系统。 在各种实施例中，参考电流选择器可以接收电池电压检测输入并输出参考电流电平信号，功率点检测检测器可以接收电源检测输入并输出功率点检查信号，以及耦合到参考电压的控制器 电流选择器和功率点检测检测器可以至少部分地基于参考电流电平信号，电池电流检测输入和功率点检查信号来接收电池电流感测输入并切换控制输出。 可以描述和/或要求保护其他实施例。

公开(公告)号：US10958163B2

公开(公告)日：2021-03-23

申请号：US16820555

申请日：2020-03-16

Applicant: Intel Corporation

Inventor： Lilly Huang ,  Christopher Schaef ,  Vaibhav Vaidya ,  Suhwan Kim

IPC: H02M3/07 ,  H02M3/158 ,  H02J7/34 ,  H02M1/00

Abstract: Apparatuses, methods and storage medium associated with deriving power output from an energy harvester are disclosed herein. In embodiments, an apparatus may include one or more processors, devices, and/or circuitry to identify a plurality of times at which an intermediate voltage of a two stage power conversion circuit corresponds to a voltage reference, and ascertain an amount of time between one of the identified times and another one of the identified times. The one or more processors, devices, and/or circuitry may derive a power or current value associated with the second power supply using the amount of time.

公开(公告)号：US10942556B2

公开(公告)日：2021-03-09

申请号：US15682724

申请日：2017-08-22

Applicant: Intel Corporation

Inventor： Dileep J. Kurian ,  Ankit Gupta ,  Akhila M ,  Tanay Karnik ,  Vaibhav Vaidya ,  David Arditti Ilitzky ,  Christopher Schaef ,  Sriram Kabisthalam Muthukumar ,  Harish K. Krishnamurthy ,  Suhwan Kim

IPC: G06F1/3203 ,  G06F1/3212 ,  G06F1/26 ,  H02J7/34 ,  H02J7/00

Abstract: Systems, apparatuses and methods may provide for early pre-charge with respect to peak power events. Application performance may improve by pre-charging a supercap just prior to initiating a system wake up from a qualified system wake-source trigger. Additionally, the pre-charging of the supercap may be controlled by a time defined pre-charge period and may also be controlled by a predetermined threshold voltage.

公开(公告)号：US10720831B2

公开(公告)日：2020-07-21

申请号：US15855683

申请日：2017-12-27

Applicant: INTEL CORPORATION

Inventor： Christopher Schaef ,  Vaibhav Vaidya ,  Suhwan Kim

IPC: H02M3/07 ,  H02M3/28 ,  H03K3/011 ,  H03B5/04

Abstract: In some examples, an apparatus for reference voltage generation includes a plurality of reference voltage rails each with a corresponding reference voltage, a first controller, and a second controller. The first controller is to cycle through the plurality of reference voltage rails and maintain the reference voltages in a synchronous mode. The second controller is to detect an event and provide an indication to the first controller to update in an asynchronous mode one of the plurality of reference voltages in response to the event. The first controller is to update in an asynchronous mode the one of the plurality of reference voltages in response to the event.