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公开(公告)号：US20240429816A1
公开(公告)日：2024-12-26
申请号：US18214031
申请日：2023-06-26
Applicant: Intel Corporation
Inventor： Nachiket Desai , Suhwan Kim
Abstract: Some embodiments include an apparatus having a first node to receive a connection from a gate of a first transistor of a voltage converter; a second node to receive a connection from a gate of a second transistor of the voltage converter; a third node to receive a connection from a node between the first and second transistors; a capacitor including a first plate coupled to the third node; a first driver including an output node coupled to the first node, a first voltage node coupled to the first plate of the capacitor, and a second voltage node coupled to a second plate of the capacitor; a second driver including an output node coupled to the second node; and a circuit including third transistors coupled in series between the second voltage node and a third voltage node.
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公开(公告)号：US11411491B2
公开(公告)日：2022-08-09
申请号：US16642853
申请日：2017-09-29
Applicant: Intel Corporation
Inventor： Vivek De , Krishnan Ravichandran , Harish Krishnamurthy , Khondker Ahmed , Sriram Vangal , Vaibhav Vaidya , Turbo Majumder , Christopher Schaef , Suhwan Kim , Xiaosen Liu , Nachiket Desai
Abstract: Voltage dividing circuitry is provided for use in a voltage converter for converting at least one input Direct Current, DC voltage to a plurality of output DC voltages. The voltage dividing circuitry including a voltage input port to receive an input DC voltage and an inductor having an input-side switch node and an output-side switch node. The output side switch node is connectable to one of a plurality of voltage output ports to supply a converted value of the input DC voltage as an output DC voltage. The flying capacitor interface has a plurality of switching elements and at least one flying capacitor, the flying capacitor interface to divide the input DC voltage to provide a predetermined fixed ratio of the input DC voltage at the input-side switch node of the inductor. A voltage converter and a power management integrated circuit having the voltage dividing circuitry are also provided.
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公开(公告)号：US20190199206A1
公开(公告)日：2019-06-27
申请号：US15855683
申请日：2017-12-27
Applicant: INTEL CORPORATION
Inventor： Christopher Schaef , Vaibhav Vaidya , Suhwan Kim
Abstract: In some examples, an apparatus for reference voltage generation includes a plurality of reference voltage rails each with a corresponding reference voltage, a first controller, and a second controller. The first controller is to cycle through the plurality of reference voltage rails and maintain the reference voltages in a synchronous mode. The second controller is to detect an event and provide an indication to the first controller to update in an asynchronous mode one of the plurality of reference voltages in response to the event. The first controller is to update in an asynchronous mode the one of the plurality of reference voltages in response to the event.
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4.发明申请公开(公告)号：US20190190725A1
公开(公告)日：2019-06-20
申请号：US15846045
申请日：2017-12-18
Applicant: Intel Corporation
Inventor： Vivek De , Krishnan Ravichandran , Harish Krishnamurthy , Khondker Ahmed , Sriram Vangal , Vaibhav Vaidya , Turbo Majumder , Christopher Schaef , Suhwan Kim , Xiaosen Liu , Nachiket Desai
IPC: H04L9/32
CPC classification number: H04L9/3278
Abstract: An apparatus is provided which comprises: an array of physically unclonable function (PUF) devices, wherein an individual device of the array comprises a magnetic junction and an interconnect, wherein the interconnect comprises a spin orbit coupling material; a circuitry to sense values stored in the array, and to provide an output; and a comparator to compare the output with a code.
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公开(公告)号：US20190103824A1
公开(公告)日：2019-04-04
申请号：US15721548
申请日：2017-09-29
Applicant: Intel Corporation
Inventor： Suhwan Kim , Vaibhav Vaidya , Christopher Schaef
Abstract: An embodiment of a harvester apparatus comprising two or more charge pump stages may include at least a first charge pump stage to receive an alternating current source, and a second charge pump stage coupled to the first charge pump stage.
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Patent Agency Ranking
6.发明申请公开(公告)号：US20190094931A1
公开(公告)日：2019-03-28
申请号：US15718991
申请日：2017-09-28
Applicant: INTEL CORPORATION
Inventor： Khondker Z. Ahmed , Vivek K. De , Nachiket V. Desai , Suhwan Kim , Harish K. Krishnamurthy , Xiaosen Liu , Turbo Majumder , Krishnan Ravichandran , Christopher Schaef , Vaibhav Vaidya , Sriram R. Vangal
Abstract: Various embodiments of the invention may analyze previous patterns of harvested energy to predict future patterns of available harvested energy. This prediction may then be used to choose from among multiple methods of energy reduction techniques. The energy reduction techniques may include multiple versions of reducing or modifying instruction execution. Reduced instruction execution may include reducing the precision of various calculations.
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公开(公告)号：US20190006939A1
公开(公告)日：2019-01-03
申请号：US15638643
申请日：2017-06-30
Applicant: INTEL CORPORATION
Inventor： Harish Krishnamurthy , Khondker Ahmed , Vivek De , Nachiket Desai , Suhwan Kim , Xiaosen Liu , Turbo Majumder , Krishnan Ravichandran , Christopher Schaef , Vaibhav Vaidya , Sriram Vangal
Abstract: Embodiments described herein describe operating a master-slave controller. Operating the master-slave controller comprises, based on a determination that the first output voltage value is greater than the second output voltage value, calculating a first duty cycle value and an input voltage value and the second voltage regulator, calculating a second duty cycle value based on the first duty cycle value, and based on a determination that the second output voltage value is greater than or equal to the first output voltage value, calculating the second duty cycle value based on the second output voltage value and the input voltage value and calculating the first duty cycle value based on the second duty cycle value and configuring the first voltage regulator with the first duty cycle value and the second voltage regulator with the second duty cycle value.
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公开(公告)号：US20170288415A1
公开(公告)日：2017-10-05
申请号：US15087613
申请日：2016-03-31
Applicant: Intel Corporation
Inventor： Vaibhav Vaidya , Suhwan Kim
IPC: H02J7/00 , H01L41/113 , H02N2/18
CPC classification number: H01L41/1136 , H02J7/0052 , H02J7/345 , H02J2007/0059 , H02N2/181 , H02N2/186
Abstract: Techniques for harvesting electrical energy from a plurality of harvesters is disclosed. An example energy harvesting system includes a plurality of harvesters and a signal conditioning circuit selectively coupled to an output of each of the plurality of harvesters. The system also includes an energy storage element coupled to the output of the signal conditioning circuit to be charged by the plurality of harvesters through the signal conditioning circuit. The system also includes a controller to discharge a selected harvester to the signal conditioning circuit when an output of the selected harvester triggers a charge collection.
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公开(公告)号：US20240421591A1
公开(公告)日：2024-12-19
申请号：US18209361
申请日：2023-06-13
Applicant: Intel Corporation
Inventor： Harshit Dhakad , Yossi Shoshany , Sergey Sofer , Suhwan Kim , Krzysztof Domanski
IPC: H02H9/04 , H01L27/02 , H03K19/003
Abstract: Techniques and mechanisms for a DC-DC voltage converter to mitigate a risk of damage to circuitry due to electrostatic discharge (ESD). In an embodiment, a protection circuit of the DC-DC voltage converter comprises a pull-up circuit and a pull-down circuit which are coupled in series between a first interconnect and a second interconnect, which are to receive a first supply voltage and a second supply voltage, respectively. A voltage divider comprises capacitors which are coupled in series with each other between the first interconnect and the second interconnect. Control circuitry is coupled with the voltage divider, and is further coupled to automatically configure a first operational mode based on an ESD event. During the first mode, the pull-up circuit is disabled and the pull-down circuit is enabled. In another embodiment, a resistor-capacitor (RC) circuit automatically transitions the protection circuit from the first mode.
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公开(公告)号：US20220065901A1
公开(公告)日：2022-03-03
申请号：US17006715
申请日：2020-08-28
Applicant: Intel Corporation
Inventor： Nachiket Desai , Harish Krishnamurthy , Suhwan Kim , Fabrice Paillet
Abstract: A current sensing topology uses an amplifier with capacitively coupled inputs in feedback to sense the input offset of the amplifier, which can be compensated for during measurement. The amplifier with capacitively coupled inputs in feedback is used to: operate the amplifier in a region where the input common-mode specifications are relaxed, so that the feedback loop gain and/or bandwidth is higher; operate the sensor from the converter input voltage by employing high-PSRR (power supply rejection ratio) regulators to create a local, clean supply voltage, causing less disruption to the power grid in the switch area; sample the difference between the input voltage and the controller supply, and recreate that between the drain voltages of the power and replica switches; and compensate for power delivery network related (PDN-related) changes in the input voltage during current sensing.
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