DEVICE, SYSTEM AND METHOD TO DELIVER POWER WITH PHASE CIRCUITS OF AN INTEGRATED CIRCUIT DIE

    公开(公告)号:US20230421040A1

    公开(公告)日:2023-12-28

    申请号:US17851997

    申请日:2022-06-28

    申请人: Intel Corporation

    IPC分类号: H02M1/00 H02M1/088 H02M3/155

    摘要: Techniques and mechanisms for facilitating a scalable delivery of current to an inductor of a voltage regulator. In an embodiment, a hardware interface of integrated circuit (IC) die accommodates coupling of the IC die to multiple inductors. The hardware interface comprises contacts which are each to couple the IC die to a respective one of the multiple inductors. A phase circuit of the IC die includes multiple cells which are each coupled to a different respective contact of a plurality of contacts of the hardware interface. A digital controller of the IC die is operable to select any of various combinations of the multiple cells each to conduct a respective current with a corresponding one of the plurality of contacts. In another embodiment, the plurality of contacts are arranged as a multi-row, multi-column array.

    Multiple input single inductor multiple output regulator

    公开(公告)号:US20170187187A1

    公开(公告)日:2017-06-29

    申请号:US14998328

    申请日:2015-12-23

    申请人: Intel Corporation

    IPC分类号: H02J3/38 H02J7/00

    摘要: A power regulator includes a plurality of harvester switches, each coupled to receive a separate energy source, a plurality of load switches, each coupled to supply power to a separate load, an inductor to store energy received from one or more energy sources and release the energy to supply the power to one or more loads and a controller to control charging of the inductor via activation of one or more of the harvester switches and discharging of the inductor via activation of one or more of the load switches.

    MAXIMUM FREQUENCY ADJUSTMENT CONTROL FOR A SWITCHED CAPACITOR POWER CONVERTER

    公开(公告)号:US20240154526A1

    公开(公告)日:2024-05-09

    申请号:US17983708

    申请日:2022-11-09

    申请人: Intel Corporation

    IPC分类号: H02M3/06 H02M1/00

    CPC分类号: H02M3/06 H02M1/0009

    摘要: A device comprises a first comparator to generate a first clock signal based on a reference voltage and a first voltage at an output of a switched-capacitor power converter (SCPC), and a second comparator to generate a first control signal based on the first voltage and a threshold voltage. A sensor is to generate a second control signal based on one of a level of a current of the first clock signal, or a duty cycle of the first clock signal. A frequency divider circuit is to generate a second clock signal based on the first control signal and the second control signal, and in some embodiments, further based on one of the first clock signal or a third clock signal. Controller circuitry is to operate switch circuitry of the SCPC based on the first clock signal.

    Fuse-less self-start controller
    5.
    发明授权

    公开(公告)号:US11336270B2

    公开(公告)日:2022-05-17

    申请号:US17006726

    申请日:2020-08-28

    申请人: Intel Corporation

    摘要: A digital self-start controller, which is functional without fuse and/or trim information. The self-start controller protects a DC-DC converter against large inrush currents and voltage overshoots, while being capable of following a variable VID (voltage identification) reference ramp imposed by the system. The self-start controller uses a relaxation oscillator to set the switching frequency of the DC-DC converter. The oscillator can be initialized using either a clock or current reference to be close to a desired operating frequency. The output of the DC-DC converter is coupled weakly to the oscillator to set the duty cycle for closed loop operation. The controller is naturally biased such that the output supply voltage is always slightly higher than a set point, eliminating the need for any process, voltage, and/or temperature (PVT) imposed trims.

    Self-tuning zero current detection circuit

    公开(公告)号:US10910946B2

    公开(公告)日:2021-02-02

    申请号:US16144961

    申请日:2018-09-27

    申请人: Intel Corporation

    IPC分类号: H02M3/158 H01L49/02 H02M1/00

    摘要: An apparatus has a comparator circuitry (e.g., auto-zero comparator) with a first input, a second input, a third input; and an output; a first device (e.g., a low-side switch) coupled to the first and second inputs of the comparator; and a circuitry (e.g., a self-tuning logic) to generate a digital code which represents a comparator offset adjustment with reference to detection of current through a second device (e.g., an inductor), wherein the digital code (e.g., a multibit digital signal) is provided to the third input of the comparator circuitry.

    PHASE CURRENT BALANCE ARCHITECTURE FOR A MULTI-PHASE POWER CONVERTER

    公开(公告)号:US20240297586A1

    公开(公告)日:2024-09-05

    申请号:US18177426

    申请日:2023-03-02

    申请人: Intel Corporation

    IPC分类号: H02M3/158 G06F1/26

    CPC分类号: H02M3/1584 G06F1/26

    摘要: Embodiments described herein may include apparatus, systems, techniques, and/or processes that are directed to multiphase power converters and how current level outputs of each phase circuit are calibrated. The multiple phase circuits are grouped into multiple subsets, wherein one phase circuit of each subset is designated as a reference phase circuit. The reference phase circuits of each subset are calibrated together, using, for example, a closed loop daisy chain technique where each reference phase circuit calibrates their current output to the current output of the previous phase circuit, or alternatively, a current averaging technique where each reference phase circuit balances their current output to the average output of the reference phase circuits. The other phase circuits in each subset calibrate their current level outputs to the reference phase circuits in their subset using, for example, an open loop daisy chain technique, a reference/follower technique or by calibrating their output to the average output of the reference phase circuits.