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1.
公开(公告)号:US20230421040A1
公开(公告)日:2023-12-28
申请号:US17851997
申请日:2022-06-28
申请人: Intel Corporation
发明人: Tamir Salus , Shunjiang Xu , Christopher Schaef
CPC分类号: H02M1/0043 , H02M1/088 , H02M3/155 , H02M1/0012
摘要: Techniques and mechanisms for facilitating a scalable delivery of current to an inductor of a voltage regulator. In an embodiment, a hardware interface of integrated circuit (IC) die accommodates coupling of the IC die to multiple inductors. The hardware interface comprises contacts which are each to couple the IC die to a respective one of the multiple inductors. A phase circuit of the IC die includes multiple cells which are each coupled to a different respective contact of a plurality of contacts of the hardware interface. A digital controller of the IC die is operable to select any of various combinations of the multiple cells each to conduct a respective current with a corresponding one of the plurality of contacts. In another embodiment, the plurality of contacts are arranged as a multi-row, multi-column array.
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2.
公开(公告)号:US10897364B2
公开(公告)日:2021-01-19
申请号:US15846045
申请日:2017-12-18
申请人: Intel Corporation
发明人: Vivek De , Krishnan Ravichandran , Harish Krishnamurthy , Khondker Ahmed , Sriram Vangal , Vaibhav Vaidya , Turbo Majumder , Christopher Schaef , Suhwan Kim , Xiaosen Liu , Nachiket Desai
IPC分类号: H04L9/32
摘要: Spin Hall Effect (SHE) magneto junction memory cells (e.g., magnetic tunneling junction (MTJ) or spin valve based memory cells) are used to implement high entropy physically unclonable function (PUF) arrays utilizing stochastics interactions of both parameter variations of the SHE-MTJ structures as well as random thermal noises. An apparatus is provided which comprises: an array of PUF devices, wherein an individual device of the array comprises a magnetic junction and an interconnect, wherein the interconnect comprises a spin orbit coupling material; a circuitry to sense values stored in the array, and to provide an output; and a comparator to compare the output with a code.
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公开(公告)号:US20170187187A1
公开(公告)日:2017-06-29
申请号:US14998328
申请日:2015-12-23
申请人: Intel Corporation
摘要: A power regulator includes a plurality of harvester switches, each coupled to receive a separate energy source, a plurality of load switches, each coupled to supply power to a separate load, an inductor to store energy received from one or more energy sources and release the energy to supply the power to one or more loads and a controller to control charging of the inductor via activation of one or more of the harvester switches and discharging of the inductor via activation of one or more of the load switches.
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公开(公告)号:US20240154526A1
公开(公告)日:2024-05-09
申请号:US17983708
申请日:2022-11-09
申请人: Intel Corporation
发明人: Keng Chen , Huanhuan Zhang , Arvind Raghavan , Tamir Salus , Christopher Schaef , Gayathri Devi Sridharan
CPC分类号: H02M3/06 , H02M1/0009
摘要: A device comprises a first comparator to generate a first clock signal based on a reference voltage and a first voltage at an output of a switched-capacitor power converter (SCPC), and a second comparator to generate a first control signal based on the first voltage and a threshold voltage. A sensor is to generate a second control signal based on one of a level of a current of the first clock signal, or a duty cycle of the first clock signal. A frequency divider circuit is to generate a second clock signal based on the first control signal and the second control signal, and in some embodiments, further based on one of the first clock signal or a third clock signal. Controller circuitry is to operate switch circuitry of the SCPC based on the first clock signal.
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公开(公告)号:US11336270B2
公开(公告)日:2022-05-17
申请号:US17006726
申请日:2020-08-28
申请人: Intel Corporation
IPC分类号: H03K3/00 , H03K3/037 , H03K5/24 , H03K17/687
摘要: A digital self-start controller, which is functional without fuse and/or trim information. The self-start controller protects a DC-DC converter against large inrush currents and voltage overshoots, while being capable of following a variable VID (voltage identification) reference ramp imposed by the system. The self-start controller uses a relaxation oscillator to set the switching frequency of the DC-DC converter. The oscillator can be initialized using either a clock or current reference to be close to a desired operating frequency. The output of the DC-DC converter is coupled weakly to the oscillator to set the duty cycle for closed loop operation. The controller is naturally biased such that the output supply voltage is always slightly higher than a set point, eliminating the need for any process, voltage, and/or temperature (PVT) imposed trims.
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公开(公告)号:US10938327B2
公开(公告)日:2021-03-02
申请号:US15721548
申请日:2017-09-29
申请人: Intel Corporation
发明人: Suhwan Kim , Vaibhav Vaidya , Christopher Schaef
摘要: An embodiment of a harvester apparatus comprising two or more charge pump stages may include at least a first charge pump stage to receive an alternating current source, and a second charge pump stage coupled to the first charge pump stage.
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公开(公告)号:US10910946B2
公开(公告)日:2021-02-02
申请号:US16144961
申请日:2018-09-27
申请人: Intel Corporation
发明人: Christopher Schaef
摘要: An apparatus has a comparator circuitry (e.g., auto-zero comparator) with a first input, a second input, a third input; and an output; a first device (e.g., a low-side switch) coupled to the first and second inputs of the comparator; and a circuitry (e.g., a self-tuning logic) to generate a digital code which represents a comparator offset adjustment with reference to detection of current through a second device (e.g., an inductor), wherein the digital code (e.g., a multibit digital signal) is provided to the third input of the comparator circuitry.
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公开(公告)号:US10320197B2
公开(公告)日:2019-06-11
申请号:US14926975
申请日:2015-10-29
申请人: Intel Corporation
发明人: Vaibhav Vaidya , Lilly Huang , Christopher Schaef
摘要: In an embodiment, a system includes controller circuitry to initiate a plurality of energy transfer cycles. Each energy transfer cycle includes an input time period during which corresponding input energy is received by a power train, and an output time period during which corresponding output energy is output from the power train. The system also includes energy detection logic to provide, upon completion of each energy transfer cycle, a corresponding indication of corresponding residual energy retained by the power train. Other embodiments are described and claimed.
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公开(公告)号:US20180267591A1
公开(公告)日:2018-09-20
申请号:US15462257
申请日:2017-03-17
申请人: INTEL CORPORATION
发明人: Dileep Kurian , Tanay Karnik , David Arditti Ilitzky , Ankit Gupta , Sriram Kabisthalam Muthukumar , Vaibhav Vaidya , Suhwan Kim , Christopher Schaef , Ilya Klochkov
IPC分类号: G06F1/32
CPC分类号: G06F1/3212 , G06F1/3287 , G06F1/329 , Y02D70/00 , Y02D70/26
摘要: The present disclosure provides for the management of power of a NZE IoT device. Managing power can include receiving the one or more asynchronous events from the asynchronous event system, determining if any of the one or more asynchronous events meet a respective charge qualification, generating the power-on command for the power-managed compute system if any of the one or more asynchronous events meet the respective charge qualification, and waiting for a power source to reach a threshold associated with the respective charge qualification if any of the one or more asynchronous events do not meet the respective charge qualification.
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公开(公告)号:US20240297586A1
公开(公告)日:2024-09-05
申请号:US18177426
申请日:2023-03-02
申请人: Intel Corporation
发明人: Keng Chen , Shunjiang Xu , Christopher Schaef , Tamir Salus , Kishan Joshi , Arvind Raghavan , Huanhuan Zhang
CPC分类号: H02M3/1584 , G06F1/26
摘要: Embodiments described herein may include apparatus, systems, techniques, and/or processes that are directed to multiphase power converters and how current level outputs of each phase circuit are calibrated. The multiple phase circuits are grouped into multiple subsets, wherein one phase circuit of each subset is designated as a reference phase circuit. The reference phase circuits of each subset are calibrated together, using, for example, a closed loop daisy chain technique where each reference phase circuit calibrates their current output to the current output of the previous phase circuit, or alternatively, a current averaging technique where each reference phase circuit balances their current output to the average output of the reference phase circuits. The other phase circuits in each subset calibrate their current level outputs to the reference phase circuits in their subset using, for example, an open loop daisy chain technique, a reference/follower technique or by calibrating their output to the average output of the reference phase circuits.
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